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1/61 february 2002 DSM2150F5V dsm (digital signal processor system memory) for analog devices dsps (3.3v supply) features summary n glueless connection to dsp C easily add memory, logic, and i/o to the ex- ternal port of adsp-218x, 219x, 2106x, 2116x, 2153x, and ts101 families of dsps from analog devices, inc. n dual flash memories C two independent flash memory arrays for storing dsp code and data C capable of read-while-write concurrent flash memory operation C device can be configured as 8-bit or 16-bit C built-in programmable address decoding logic allows mapping individual sectors of each flash array to any address boundary C each flash sector can be write protected n 512 kbyte main flash memory C ample storage for boot loading dsp code/ data upon reset and subsequent code swaps C large capacity for storing tables and con- stants or for data recording n 32 kbyte secondary flash memory C smaller sector size ideal for storing calibra- tion and configuration constants. eliminate external serial eeprom. C optionally bypass internal dsp boot rom during start-up and execute code directly from secondary flash. use for custom start-up code and in-application programming (iap). n up to 40 multifunction i/o pins C increase total dsp system i/o capability C i/o controlled by dsp software or pld logic n general purpose pld C use for peripheral glue logic to keypads, con- trol panel, displays, lcds, and other devices C over 3,000 gates of pld with 16 macro cells C eliminate plds and external logic devices C create state machines, chip selects, simple shifters and counters, clock dividers, delays C simple psdsoft express tm development soft- ware, free from www.st.com/psd figure 1. packages n in-system programming (isp) with jtag C program entire chip in 15-35 seconds with no involvement of the dsp C optionally links with dsp jtag debug port C eliminate need for sockets and pre-program- ming of memory and logic devices C isp allows efficient manufacturing and prod- uct testing supporting just-in-time inventory C use low-cost flashlink tm cable with any pc. available from www.st.com/psd . n content security C programmable security bit blocks access of device programmers and readers n operating range C vcc: 3.3v 10%, temp: C40 o c to +85 o c n zero-power technology C50 m a standby current typical n flash memory speed, endurance, retention C 120 ns, 100k cycles, 15 year retention tqfp80 (t)
DSM2150F5V 2/61 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dsp address/data/control interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 main flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 secondary flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 programmable logic (plds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 runtime control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 memory page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 jtag isp port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 security and nvm sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 runtime control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 flash memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 instruction sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 reading flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 programming flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 decode pld (dpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 complex pld (cpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 dsp bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ports a, b and c C functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 port d C functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 port e C functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 port f C functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 port g C functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/61 DSM2150F5V power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 power on reset, warm reset, power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 programming in-circuit using jtag isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 ac/dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table: operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table: dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table: cpld combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table: cpld microcell synchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table: cpld microcell asynchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table: input microcell timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table: read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table: write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table: flash memory program, write and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table: reset (reset) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table: isc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table: tqfp80 - 80 lead plastic quad flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table: pin assignments C tqfp80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table: ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 appendix a. csiop register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table: data-in registers C ports a, b, c, d, e, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table: data-out registers C ports a, b, c, d, e, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table: direction registers C ports a, b, c, d, e, g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table: drive registers C ports a, b, e, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table: drive registers C port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table: enable-out registers C ports a, b, c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table: input macrocells C ports a, b, c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table: output macrocells a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table: output macrocells b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table: mask macrocells a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table: mask macrocells b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table: flash memory protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 table: flash boot protection register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table: jtag enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table: page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table: pmmr0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table: pmmr2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table: memory_id0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DSM2150F5V 4/61 appendix b. typical connections, DSM2150F5V and adsp-21535 blackfin dsp. . . . . . 52 typical memory map, DSM2150F5V and adsp21535 blackfin dsp . . . . . . . . . . . . . . . . . . . . 53 specifying the memory map with psdsoft expresstm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 appendix c. typical connections, DSM2150F5V and adsp-21062 sharc dsp . . . . . . . . 55 appendix d. typical connections, DSM2150F5V and adsp-ts101s tigersharc dsp . 56 appendix e. typical connections, DSM2150F5V and adsp-2191. . . . . . . . . . . . . . . . . . . . . 57 appendix f. typical connections, DSM2150F5V and adsp-2188m . . . . . . . . . . . . . . . . . . . 58
5/61 DSM2150F5V summary description the DSM2150F5V is an 8 or 16-bit system mem- ory device for use with the analog devices dsps. dsm means digital signal processor system memory. a dsm device brings in-system pro- grammable (isp) flash memory, parameter stor- age, programmable logic, and additional i/o to dsp systems. the result is a flexible two-chip so- lution for dsp designs. on-chip integrated memo- ry decode logic makes it easy to map dual banks of flash memory to the dsps in a variety of ways for bootloading or bypassing dsp boot rom, code execution, data recording, code swapping, and parameter storage. jtag isp reduces development time, simplifies manufacturing flow, and lowers the cost of field up- grades. the jtag isp interface eliminates the- need for sockets and pre-programmed memory and logic devices. end products may be manufac- tured with a blank dsm device soldered down and programmed at the end of the assembly line in 15 to 35 seconds with no involvement of the dsp. rapidly program test code, then application code as determined by just-in time inventory require- ments. additionally, jtag isp reduces develop- ment time by turning fast iterations of dsp code in the lab. the dsm jtag interface may be option- ally chained with the dsp jtag debug interface (except adsp-218x). code updates in the field re- quire no product disassembly. the flashlink tm jtag programming cable costs $59 usd and plugs into any pc parallel port. programming through conventional device insertion program- mers is also available using psdpro from stmi- croelectronics and other 3rd party programmers. see www.st.com/psd . dsm devices add programmable logic (pld) and up to 32 configurable i/o pins to the dsp system. the state of i/o pins can be driven by dsp soft- ware or pld logic. pld and i/o configuration are programmable by jtag isp. the pld consists of more than 3000 gates and has 16 macro cell reg- isters. common uses for the pld include chip-se- lects for external devices, state-machines, simple shifters and counters, keypad and control panel in- terfaces, clock dividers, handshake delay, muxes, etc., eliminating the need for small external plds and logic devices. configuration of pld, i/o, and flash memory mapping is easily entered in a point-and-click environment using the software development tool, psdsoft express tm , available at no charge from www.st.com/psd. the two-chip dsp/dsm combination is ideal for systems having limitations on size, emi levels, and power con- sumption. dsm memory and logic are zero-pow- er, meaning they automatically go to standby between memory accesses or logic input chang- es, producing low active and standby current con- sumption, which is ideal for battery powered products. a programmable security bit in the dsm protects its contents from unauthorized viewing and copy- ing. when set, the security bit will block access of programming devices (jtag or others) to the dsm flash memories and pld configuration. the only way to defeat the security bit is to erase the entire dsm device, after which the device is blank and may be used again. the dsp will always have access to flash memory contents through the data bus, even with security bit set. figure 2. system block diagram, two chip solution ai05732 addr & decode logic primary flash memory 512k bytes 16 macrocell pld i/o control power management content security jtag isp to all areas i/o bus address 8or16data control DSM2150F5V dsp system memory analog devices dsp adsp-218x adsp-219x adsp-2153x adsp-2106x adsp-2116x adsp-ts101s jtag isp jtag debug (all but adsp-218x family) secondary flash memory 32k bytes i/o flags sdram host mcu serial device serial device 16 i/o ports with pld i/o, pld, chip selects 8to16 i/o ports general purpose i/o
DSM2150F5V 6/61 table 1. DSM2150F5V dsp memory system devices table 2. compatible analog devices dsps part number main flash memory secondary flash mem pld i/o ports v cc and i/o mem speed package op temp DSM2150F5V-12t6 512 kbytes, eight 64kbyte sectors 32 kbytes, four 8 kbyte sectors 16 macro cells up to 40 3.3v 10% 120 ns 80-pin tqfp C40 o c to +85 o c dsp part number core operating voltage i/o voltage adsp-2183, 2184l, 2185l, 2186l, 2187l 3.3v 3.3v adsp-2185m, 2186m, 2188m, 2189m 2.5v 3.3v adsp-2184n, 2185n, 2186n, 2187n, 2188n, 2189n 1.8v 3.3v adsp-2191m, 2195m, 2196m 2.5v 3.3v blackfin adsp-21532s 3.3v 3.3v blackfin adsp-21535p 1.5v 3.3v sharc adsp-21060l, 21061l, 21062l, 21065l 3.3v 3.3v sharc adsp-21160m 2.5v 3.3v sharc adsp-21160n, 21161n 1.8v 3.3v tiger sharc adsp-ts101s 1.0v 3.3v
7/61 DSM2150F5V figure 3. tqfp connections 60 cntl1 59 cntl0 58 pa7 57 pa6 56 pa5 55 pa4 54 pa3 53 pa2 52 pa1 51 pa0 50 gnd 49 gnd 48 pc7 47 pc6 46 pc5 45 pc4 44 pc3 43 pc2 42 pc1 41 pc0 pd2 pd3 ad0 ad1 ad2 ad3 ad4 gnd v cc ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pd1 pd0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 gnd v cc pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 v cc gnd pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 reset cntl2 ai04943
DSM2150F5V 8/61 architectural overview major functional blocks are shown in figure 4. dsp address/data/control interface these dsp signals attach directly to the dsm for a glueless connection. an 8-bit or 16-bit data con- nection is formed and 16 or more dsp address lines can be decoded as well as various dsp memory strobes; i.e. bms , rd , awe , ioms , msx , etc. the data path width must be specified as 8- bits or 16-bits in psdsoft express. this configura- tion is a static, meaning the data path width cannot switch between 8-bits and 16-bits during runtime. port f is used for 8-bit data path, ports f and g are used for 16-bit data path. there are many different ways the dsm2150f5 can be configured and used depending on system requirements. see appendi- ces for example connections between the dsm2150 and different dsps. figure 4. block diagram main flash memory the 4m bit (512 kbyte) main flash memory is di- vided into eight equally-sized 64 kbyte sectors that are individually selectable through the de- code pld. each flash memory sector can be lo- cated at any address as defined by the user with psdsoft express. dsp code and data are easily placed in flash memory using psdsoft express, the software development tool. secondary flash memory the 256 kbit (32 kbyte) secondary flash memory is divided into eight equally-sized 8 kbyte sectors that are individually selectable through the de- code pld. each flash memory sector can be lo- cated at any address as defined by the user with psdsoft express. dsp code and data can also be placed secondary flash memory using the psd- soft express development tool. pd0 pd1 pd2 i/o port pd3 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 i/o port pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 i/o port general pld 24 input microcells 16 output microcells aa aaaaaa bbbbbbbb page reg security lock pld input bus pin feedback node feedback DSM2150F5V dsp system memory decode pld and array fs0-7 aaaaaaaa bbb bbbbb c c c c c c c c to pld in bus pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 i/o port jtag isp controller internal addr, data, control bus linked to dsp internal addr, data, control bus linked to dsp ad0 dsp addr ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 dsp cntl cntl2 rst\ cntl0 cntl1 runtime control gpio power mngmt csiop pld csboot0-3 secondary flash 4 blocks, 8 kb 32 kbytes total main flash 8 blocks, 64 kb 512 kbytes total ecs0-7 dsp data pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 dsp data or gp i/o pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 i/o port
9/61 DSM2150F5V secondary flash memory is good for storing data because of its smaller sectors. software eeprom emulation techniques can be used for small data sets that change frequently on a byte-by-byte ba- sis. secondary flash may also be used to store custom start-up code for applications that do not boot us- ing dma, but instead start executing code from ex- ternal memory upon reset (bypass internal dsp boot rom). storing code here can keep the entire main flash free of initialization code for clean soft- ware partitioning. if only one or more 8 kbyte sec- tors are needed for start-up code, the remaining sectors of secondary flash may be used for data storage. in-application-programming (iap) may be imple- mented using secondary flash. for example, code to implement iap over a usb channel may be stored here. the dsp executes code from sec- ondary flash array while erasing and writing new code to the main flash array as it is received over the usb channel. any communication channel that the dsp supports can be used for iap. secondary flash may also be used as an exten- sion to main flash memory producing a total of 544 kbytes miscellaneous: main and secondary flash memo- ries are totally independent, allowing concurrent operation. the dsp can read from one memory while erasing or programming the other. the dsp can erase flash memories by individual sectors or the entire flash memory array may be erased at one time. each sector in either flash memory ar- ray may be individually write protected, blocking any writes from the dsp (good for boot and start- up code protection). the flash memories auto- matically go to standby between dsp read or write accesses to conserve power. maximum access times include sector decoding time. maximum erase cycles is 100k and data retention is 15 years minimum. flash memory, as well as the en- tire dsm device may be programmed with the jtag isp interface with no dsp involvement. programmable logic (plds) the dsm family contains two plds that may op- tionally run in turbo or non-turbo mode. plds op- erate faster (less propagation delay) while in turbo mode but consume more power than non- turbo mode. non-turbo mode allows the plds to automatically go to standby when no inputs are change to conserve power. the turbo mode set- ting is controlled at runtime by dsp software. decode pld (dpld). this is programmable log- ic used to select one of the eight individual main flash memory segments, one of four individual secondary flash memory segments, or the group of control registers within the dsm device. the dpld can also drive external chip select signals on port c pins. dpld input signals include: dsp address and control signals, page register out- puts, dsm port pins, cpld logic feedback. complex pld (cpld). this programmable logic is used to create both combinatorial and sequen- tial general purpose logic. the cpld contains 16 output macrocells (omcs) and 24 input macro- cells (imcs). psd macrocell registers are unique in that that have direct connection to the dsp data bus allowing them to be loaded and read directly by the dsp at runtime. this direct access is good for making small peripheral devices (shifters, counters, state machines, etc.) that are accessed directly by the dsp with little overhead. dpld in- puts include dsp address and control signals, page register outputs, dsm port pins, and cpld feedback. omcs: the general structure of the cpld is simi- lar in nature to a 22v10 pld device with the famil- iar sum-of-products (and-or) construct. true and compliment versions of 73 input signals are available to a large and array. and array outputs feed into a multiple product-term or gate within each omc (up to 10 product-terms for each omc). logic output of the or gate can be passed on as combinatorial logic or combined with a flip- flop within in each omc to realize sequential logic. omcs can be used as a buried nodes with feed- back to the and array or omc output can be rout- ed to pins on port a or port b. imcs: inputs from pins on ports a, b or c are rout- ed to imcs for conditioning (clocking or latching) as they enter the chip, which is good for sampling and debouncing inputs. alternatively, imcs can pass port input signals directly to pld inputs with- out clocking or latching. the dsp may read the imcs at any time. runtime control registers a block of 256 bytes is decoded inside the dsm device for control and status registers. 50 registers are used from the block of 256 locations to control the output state of i/o pins, to read i/o pins, to con- trol power management, to read/write macrocells, and other functions at runtime. see table 4 for de- scription. the base address of these 256 locations is referred to in this data sheet as csiop (chip se- lect i/o port). individual registers within this block are accessed with an offset from the base ad- dress. some dsps can access csiop registers us- ing i/o memory with the ioms strobe (if equipped). csiop registers are bytes. when the dsm is config- ured for 16-bit operation, csiop registers are read in byte pairs at even addresses only. care should be taken while writing csiop registers to ensure the proper byte is written within the byte pair. this is not a problem for dsps that support the bhe (byte high enable) signal on the cntl2 input pin, or
DSM2150F5V 10/61 wrl , wrh (write low byte, write high byte) on the cntl0 and pd3 input pins of the DSM2150F5V. memory page register this 8-bit register can be loaded and read by the dsp at runtime as one of the csiop registers. its outputs feed directly into both plds. the page register can be used for special memory mapping requirements and also for general logic. i/o ports the dsm has 52 individually configurable i/o pins distributed over the seven ports (ports a, b, c, d, e, f, and g). at least 32 i/o are available when dsm2150f5 is connected with 8-bit data path, and at least 24 i/o are available with 16-bit data path. each i/o pin can be individually configured for dif- ferent functions such as standard mcu i/o ports or pld i/o on a pin by pin basis. (mcu i/o means that for each pin, its output state can be controlled or its input value can be read by the dsp at runt- ime using the csiop registers like an mcu would do.) the static configuration of all port pins is defined with the psdsoft express tm software develop- ment tool. the dynamic action of the ports pins is controlled by dsp runtime software. jtag isp port in-system programming (isp) can be performed through the jtag signals on port e. this serial in- terface allows programming of the entire dsm de- vice or subsections (that is, only flash memory but not the plds) without the participation of the dsp. a blank dsm device soldered to a circuit board can be completely programmed in 15 to 35 sec- onds. the basic jtag signals; tms, tck, tdi, and tdo form the ieee-1149.1 interface. the dsm device does not implement the ieee- 1149.1 boundary scan functions. the dsm uses the jtag interface for isp only. however, the dsm device can reside in a standard jtag chain with other jtag devices and it will remain in bypass mode while other devices perform boundary scan. isp programming time can be reduced as much as 30% by using two more signals on port e, tstat and terr in addition to tms, tck, tdi and tdo. the flashlink tm jtag programming cable is available from stmicroelectronics for $usd59 and psdsoft express software is available at no charge from www.psdst.com. that is all that is needed to program a dsm device using the paral- lel port on any pc or note-book. see section titled programming in-circuit using jtag isp on page 33. power management the dsm has bits in csiop registers that are con- figured at run-time by the dsp to reduce power consumption of the cpld. the turbo bit in the pmmr0 register can be set to logic 1 and the cpld will go to non-turbo mode, meaning it will latch its outputs and go to sleep until the next tran- sition on its inputs. there is a slight penalty in pld performance (longer propagation delay), but sig- nificant power savings are realized. additionally, other bits in two csiop registers can be set by the dsp to selectively block signals from entering the cpld which reduces power con- sumption. both flash memories automatically go to standy current between accesses. no user action re- quired. security and nvm sector protection a programmable security bit in the dsm protects its contents from unauthorized viewing and copy- ing. when set, the security bit will block access of programming devices (jtag or others) to the dsm flash memory and pld configuration. the only way to defeat the security bit is to erase the entire dsm device, after which the device is blank and may be used again. additionally, the contents of each individual flash memory sector can be write protected (sector pro- tection) by configuration with psdsoft express tm . this is typically used to protect dsp boot code from being corrupted by inadvertent writes to flash memory from the dsp. pin assignments pin assignment are shown for the 80-pin tqfp- package in figure 3, and their description in table 3.
11/61 DSM2150F5V table 3. pin description pin name type description ad0-15 in sixteen address inputs from the dsp. cntl0 in active low write strobe input from the dsp, typically connected to dsp wr signal. also functions as wrl for dsps which use wrl strobe when writing low byte only in 16-bit word. cntl1 in active low read strobe input from the dsp. cntl2 in programmable control input. cntl2 may be used for bhe (byte high enable) when dsm2150f5 is configured for 16-bit operation. bhe = 0 will allow a byte write from data lines d8-d15 ignoring data lines d0-d7. bhe = 1 will allow a byte write from d0-d7 ignoring datalines d8-d15. dsp read operatons are not affected by bhe (always read both bytes). reset in active low reset input from system. resets dsm i/o ports, page register contents, and other dsm configuration registers. must be logic low at power-up. pa0-7 i/o eight configurable port a signals with the following functions: 1. mcu i/o C dsp may write or read pins directly at runtime with csiop registers. 2. cpld output macrocell (mcella0-7) outputs. 3. inputs to the plds (via input macrocells). can be used to input address a16 and above. note: pa0-pa7 may be configured at run-time as standard cmos or open drain outputs. pb0-7 i/o eight configurable port b signals with the following functions: 1. mcu i/o C dsp may write or read pins directly at runtime with csiop registers. 2. cpld output macrocell (mcellb0-7 or mcellc0-7) outputs. 3. inputs to the plds (via input macrocells). can be used to input address a16 and above. note: pb0-pb7 may be configured at run-time as standard cmos or open drain outputs. pc0-7 i/o eight configurable port c signals with the following functions: 1. mcu i/o C dsp may write or read pins directly at runtime with csiop registers. 2. dpld chip-select outputs (ecs0-7, does not consume microcells). 3. inputs to the plds (via input macrocells). can be used to input address a16 and above. note: pc0-pc7 may be configured at run-time as standard cmos or faster slew rate output. pd0-3 i/o four configurable port d signals with the following functions: 1. mcu i/o C dsp may write or read pins directly at runtime with csiop registers. 2. input to the plds (no associated input macrocells, routes directly into plds). can be used to input address a16 and above. 3. pd1 can be configured as clkin, a common clock input to pld. 4. pd2 can be configured as csi , active low chip select input to select flash memory. flash memory is disabled to conserve more power when csi is logic high. 5. pd3 can be used for wrh strobe from dsp to write high byte only for 16-bit configuration. pe0-7 i/o eight configurable port e signals with the following functions: 1. mcu i/o C dsp may write or read pins directly at runtime with csiop registers. 2. pe0, pe1, pe2, and pe3 can form the jtag ieee-1149.1 isp serial interface as signals tms, tck, tdi, and tdo respectively. 3. pe4 and pe5 can form the enhanced jtag signals tstat and terr respectively. reduces isp programming time up to 30% when used in addition to the standard four jtag signals: tdi, tdo, tms, tck. 4. pe4 can be configured as the ready/busy output to indicate flash memory programming status during parallel programming. may be polled by dsp or used as dsp interrupt. note 1: pe0-pe7 may be configured at run-time as either standard cmos or open drain outputs. note 2: the jtag isp pins may be multiplexed with other i/o functions. pf0-7 i/o port f connects to eight data bus signals, d0 - d7 from dsp. pg0-7 i/o port g connects to eight data bus signals, d8 - d15 from dsp if 16-bit data path is used. otherwise, pg0-pg7 can be used for general purpose mcu i/o pins. note: pg0-pg7 may be configured at run-time as standard cmos or open drain outputs. v cc supply voltage gnd ground pins
DSM2150F5V 12/61 runtime control register definition a block of 256 addresses are decoded inside the dsm2150f5 for control and status. 50 locations contain registers that the dsp accesses at runt- ime. the base address of the registers is called csiop (chip select i/o port). table 4 lists the reg- isters and their offsets (in hexadecimal) from the csiop base. see appendix a for bit definitions. note: 1. do not write to unused locations, they should remain logic zero. 2. see table 13 for register state at reset and at power-on. table 4. csiop registers and their offsets (in hexadecimal) register name port a port b port c port d port e port g oth er description data in 00 01 10 11 30 41 mcui/o input mode. read to obtain current logic level of port pins. no writes. data out 04 05 14 15 34 45 mcu i/o output mode. write to set logic level on port pins. read to check status. direction 06 07 16 17 36 47 mcu i/o mode. configures port pin as input or output. write to set direction of port pins. logic 1 = out, logic 0 = in. read to check status. drive select 08 09 18 19 38 49 write to configure port pins as either standard cmos or open drain on some pins, while selecting high slew rate on other pins. read to check status. input macrocells 0a 0b 1a read to obtain state of imcs. no writes. enable out 0c 0d 1c read to obtain the status of the output enable logic on each i/o port driver. no writes. output macrocells a 20 read to get logic state of output of omc bank a. write to load registers of omc bank a. output macrocells b 21 read to get logic state of output of omc bank b. write to load registers of omc bank b. mask macrocells a 22 write to set mask for loading omcs in bank a. logic 1 in a bit position will block reads/writes of the corresponding omc. logic 0 will pass omc value. read to check status. mask macrocells b 23 write to set mask for loading omcs in bank b. logic 1 in a bit position will block reads/writes of the corresponding omc. logic 0 will pass omc value. read to check status. main flash sector protect c0 read to determine main flash sector protection setting. no writes. security bit and secondary flash sector protection c2 read to determine if dsm devices security bit is active. logic 1 = device secured. also read to determine secondary flash protection setting status. no writes. jtag enable c7 write to enable jtag pins (optional feature). read to check status. pmmr0 b0 power management register 0. write and read. pmmr2 b4 power management register 2. write and read. page e0 memory page register. write and read. memory_id0 f0 read to get size of main flash memory. no writes. memory_id1 f1 read to get size of 2nd flash memory. no writes.
13/61 DSM2150F5V detailed operation figure 4 shows major functional areas of the de- vice: n flash memories n plds (dpld, cpld, page register) n dsp bus interface (address, data, control) n i/o ports n runtime control registers n jtag isp interface the following describes these functions in more detail. flash memories the main flash memory array is divided into eight equal 64 kbyte sectors. the secondary flash memory array is divided into four equal 8 kbyte sectors. each sector is selected by the dpld can be separately protected from program and erase cycles. this configuration is specified by using ps- dsoft express tm . memory sector select signals. the dpld gen- erates the select signals for all the internal memo- ry blocks (see figure 7). each of the twelve sectors of the flash memories has a select signal ( fs0-fs7, or csboot0-csboot3 ) which con- tains up to three product terms. having three prod- uct terms for each select signal allows a given sector to be mapped into multiple areas of system memory if needed. ready/busy (pe4). this signal can be used to output the ready/ busy status of the device. ready/ busy is a 0 (busy) when either flash memory array is being written, or when either flash memory ar- ray is being erased. the output is a 1 (ready) when no write or erase cycle is in progress. this signal may be polled by the dsp or used as a dsp interrupt to indicate when an erase or program cy- cle is complete. memory operation. the flash memories are ac- cessed through the dsp address, data, and con- trol bus interface. dsps and mcus cannot write to flash memory as it would an sram device. flash memory must first be unlocked with a special sequence of write op- erations to invoke an internal algorithm, then a sin- gle data byte (or word if dsm2150f5 is configured for 16-bit operation) is written to the flash memory array, then programming status is checked by a read operation or by checking the ready/ busy pin (pe4). this unlocking sequence optionally may be bypassed by using the unlock bypass com- mand to reduce programming time . table 5 lists all of the special instruction sequenc- es to program (write) data to the flash memory ar- rays, erase the arrays, and check for different types of status from the arrays when the dsm2150f5 is configured to operate as an 8-bit device. table 6 lists instruction sequences when the dsm2150 is configured for 16-bit operation. these instruction sequences are different combi- nations of individual write and read operations. important: the dsp cannot read and execute code from the same flash memory array for which it is directing an instruction sequence. or more simply stated, the dsp may not read code from the same flash array that is writing or erasing. in- stead, the dsp must execute code from an alter- nate memory (like its own internal sram or a different flash array) while sending instructions to a given flash array. since the two flash memory arrays inside the dsm device are completely inde- pendent, the dsp may read code from one array while sending instructions to the other. after a flash memory array is programmed (writ- ten) it will go to read array mode, then the dsp can read from flash memory just as if would from any rom or sram device.
DSM2150F5V 14/61 table 5. instruction sequences for 8-bit operaton 1,2,3,4 note: 1. all values are in hexadecimal, x = dont care 2. a desired internal flash memory sector select signal (fs0 - fs7 or csboot0 - csboot3) must be active for each write or read cycle. only one of these sector select signals will be active at any given time depending on the address presented by the dsp a nd the memory mapping defined in psdsoft express. fs0 - fs7 and csboot0-csboot3 are active high logic internally. 3. only address bits a11-a0 are used during flash memory instruction sequence decoding bus cycles. the individual sector select signal (fs0 - fs7 or csboot0-csboot3) which is active during the instruction sequences determines the complete address. 4. for write operations, addresses are latched on the falling edge of write strobe (wr , cntl0), data is latched on the rising edge of write strobe (wr , cntl0) 5. no unlock or instruction cycles are required when the device is in the read array mode. operation is like reading a rom devic e. 6. the reset flash instruction is required to return to the normal read array mode if the error flag (dq5) bit goes high, or aft er read- ing the flash identifier or after reading the sector protection status. 7. the dsp cannot invoke this instruction sequence while executing code from the same flash memory as that for which the instruc - tion sequence is intended. the dsp must fetch, for example, the code from the dsp sram when reading the flash memory iden- tifier or sector protection status. 8. the data is 00h for an unprotected sector, and 01h for a protected sector. in the fourth cycle, the sector select is active, and (a1,a0)=(1,0) 9. directing this command to any individual active flash memory segment (fs0 - fs7) will invoke the bulk erase of all eight flas h memory sectors. likewise, directing command to any secondary flash sector (csboot0-3) will invoke erase of all four sectors. 10. dsp writes command sequence to initial segment to be erased, then writes the byte 30h to additional sectors to be erased. 30 h must be addressed to one of the other flash memory segments (fs0-7 or csboot0-3) for each additional segment (write 30h to any address within a desired sector). no more time than t timeout can elapse between subsequent additional sector erase com- mands. 11. the system may perform read and program cycles in non-erasing sectors, read the flash id or read the sector protect status, when in the suspend sector erase mode. the suspend sector erase instruction sequence is valid only during a sector erase cycle. 12. the resume sector erase instruction sequence is valid only during the suspend sector erase mode. 13. the unlock bypass instructionis required prior to the unlock bypass program instruction. 14. the unlock bypass reset flash instruction is required to return to reading memory data when the device is in umlock bypass m ode. instruction sequence cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read memory contents 5 read byte from any valid flash memory addr read flash identifier (main flash only) 6,7 write aah to xx555h write 55h to xxaaah write 90h to xx555h read identifier at addr xxx01h read memory sector protection status 6,7,8 write aah to xx555h write 55h to xxaaah write 90h to xx555h read value at addr xxx02h program a flash byte write aah to xx555h write 55h to xxaaah write a0h to xx555h write (program) data to addr flash bulk erase 9 write aah to xx555h write 55h to xxaaah write 80h to xx555h write aah to xx555h write 55h to xxaaah write 10h to xx555h flash sector erase 10 write aah to xx555h write 55h to xxaaah write 80h to xx555h write aah to xx555h write 55h to xxaaah write 30h to another sector write 30h to another sector suspend sector erase 11 write b0h to addr in fs0-7 or csboot0-3 resume sector erase 12 write 30h to addr in fs0-7 or csboot0-3 reset flash 6 write f0h to addr in fs0-7 or csboot0-3 unlock bypass write aah to xx555h write 55h to xxaaah write 20h to xx555h unlock bypass program 13 write a0h to addr in fs0-7 or csboot0-3 write (program) data to addr unlock bypass reset 14 write 90h to addr in fs0-7 or csboot0-3 write 00h to addr in fs0-7 or csboot0-3
15/61 DSM2150F5V table 6. instruction sequences for 16-bit operaton 1,2,3,4,15 note: 1. all values are in hexadecimal, x = dont care 2. a desired internal flash memory sector select signal (fs0 - fs7 or csboot0 - csboot3) must be active for each write or read cycle. only one of these sector select signals will be active at any given time depending on the address presented by the dsp a nd the memory mapping defined in psdsoft express. fs0 - fs7 and csboot0-csboot3 are active high logic internally. 3. only address bits a11-a0 are used during flash memory instruction sequence decoding bus cycles. the individual sector select signal (fs0 - fs7 or csboot0-csboot3) which is active during the instruction sequences determines the complete address. 4. for write operations, addresses are latched on the falling edge of write strobe (wr , cntl0), data is latched on the rising edge of write strobe (wr , cntl0) 5. no unlock or instruction cycles are required when the device is in the read array mode. operation is like reading a rom devic e. 6. the reset flash instruction is required to return to the normal read array mode if the error flag (dq5) bit goes high, or aft er read- ing the flash identifier or after reading the sector protection status. 7. the dsp cannot invoke this instruction sequence while executing code from the same flash memory as that for which the instruc - tion sequence is intended. the dsp must fetch, for example, the code from the dsp sram when reading the flash memory iden- tifier or sector protection status. 8. the data is xx00h for an unprotected sector, and xx01h for a protected sector. in the fourth cycle, the sector select is acti ve, and (a1,a0)=(1,0) 9. directing this command to any individual active flash memory segment (fs0 - fs7) will invoke the bulk erase of all eight flas h memory sectors. likewise, directing command to any secondary flash sector (csboot0-3) will invoke erase of all four sectors. 10. dsp writes command sequence to initial segment to be erased, then writes the word xx30h to additional sectors to be erased. xx30h must be addressed to one of the other flash memory segments (fs0-7 or csboot0-3) for each additional segment (write xx30h to any address within a desired sector). no more time than t timeout can elapse between subsequent additional sector erase commands. 11. the system may perform read and program cycles in non-erasing sectors, read the flash id or read the sector protect status, when in the suspend sector erase mode. the suspend sector erase instruction sequence is valid only during a sector erase cycle. 12. the resume sector erase instruction sequence is valid only during the suspend sector erase mode. 13. the unlock bypass instructionis required prior to the unlock bypass program instruction. 14. the unlock bypass reset flash instruction is required to return to reading memory data when the device is in umlock bypass m ode. 15. all bus cycles in an instruction sequence are writes or reads to an even address (xxaaah or xx554h), and only the low byte, d0- d7, is significant (upper byte on d8-d15 is ignored). a flash memory program bus cycle writes a word to an even address. instruction sequence cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read memory contents 5 read word from even addr read flash identifier (main flash only) 6,7 write xxaah to xxaaah write xx55h to xx554h write xx90h to xxaaah read identifier at addr xxx02h read sector protectstatus 6,7,8 write xxaah to xxaaah write xx55h to xx554h write xx90h to xxaaah read value at addr xxx04h program a flash word write xxaah to xxaaah write xx55h to xx554h write xxa0h to xxaaah write word to even address flash bulk erase 9 write xxaah to xxaaah write xx55h to xx554h write xx80h to xxaaah write xxaah to xxaaah write xx55h to xx554h write xx10h to xxaaah flash sector erase 10 write xxaah to xxaaah write xx55h to xx554h write xx80h to xxaaah write xxaah to xxaaah write xx55h to xx554h write xx30h to new sectr write xx30h to new sector suspend sector erase 11 write xxb0h to even addr in fs0- 7 or csboot0-3 resume sector erase 12 write xx30h to even addr in fs0- 7 or csboot0-3 reset flash 6 write xxf0h to even addr in fs0- 7 or csboot0-3 unlock bypass write xxaah to xxaaah write xx55h to xx554h write xx20h to xxaaah unlock bypass program 13 write xxa0h to even addr in fs0- 7 or csboot0-3 write word to even addr unlock bypass reset 14 write xx90h to even addr in fs0- 7 or csboot0-3 write xx00h to even addr in fs0- 7 or csboot0-3
DSM2150F5V 16/61 instruction sequences an instruction sequence consists of a sequence of specific write or read operations. important: when the dsm2150f5 is configured for 8-bit oper- ations, all instruction sequences consist of byte write and read operations on an even or odd ad- dress boundary. flash memory locations are pro- grammed in bytes to even or odd addresses. when the dsm2150f5 is configured for 16-bit op- eration, all instruction sequences consist of word write and read operations on even address bound- aries only. the lower byte on d0-7 is significant and the upper byte on d8-15 is ignored during in- structions and status. flash memory locations are programmed in 16-bit words to even addresses only. each byte/word written to the device is received and sequentially decoded and not executed as a standard write operation to the memory array until the entire command string has been received. the instruction sequence is executed when the correct number of bytes/words are properly received and the time between two consecutive bytes/words is shorter than the time-out period, t timeout . some instruction sequences are structured to include read operations after the initial write operations. the instruction sequence must be followed exact- ly. any invalid combination of instruction bytes/ words or time-out between two consecutive bytes/ words while addressing flash memory resets the device logic into read array mode (flash memory is read like a rom device). the device supports the instruction sequences summarized in table 5 and table 6: flash memory: n read memory contents n read main flash identifier value n read sector protection status n program a byte/word n erase memory by chip or sector n suspend or resume sector erase n reset to read array mode n unlock bypass instructions for efficient decoding of the instruction sequenc- es, the first two bytes/words of an instruction se- quence are the coded cycles and are followed by an instruction byte/word or confirmation byte/ word. the coded cycles consist of writing the data aah to address xx555h (or x xaah to address xxaaah for 16-bit mode) during the first cycle and data 55h to address x xaaah (or xx55h to ad- dress xx554 for 16-bit mode) during the second cycle. address inpur signals a12 and above are dont care during the instruction sequence write cycles. however, the appropriate internal sector select ( fs0-fs7 or csboot0-csboot3 ) must be selected internally (active is logic 1). reading flash memory under typical conditions, the dsp may read the flash memory using read operations just as it would a rom or ram device. alternately, the dsp may use read operations to obtain status informa- tion about a program or erase cycle that is cur- rently in progress. lastly, the dsp may use instruction sequences to read special data from these memory blocks. the following sections de- scribe these read instruction sequences. read memory contents. flash memory is placed in the read array mode after power-up, chip reset, or a reset flash memory instruction sequence (see table 5 or 6). the dsp can read the memory contents of the flash memory by us- ing read operations any time the read operation is not part of an instruction sequence. bytes are read from even or odd addresses when the dsm2150f5 is configured for 8-bit operation. only 16-bit words are read from even addresses when the dsm2150f5 is configured for 16-bit opera- tions. read main flash identifier. the main flash memory identifier is read with an instruction se- quence composed of 4 operations: 3 specific write operations and a read operation (see table 5 or 6). during the read operation the appropriate inter- nal sector select ( fs0-fs7 ) must be active. the identifier is e8h (or xxe8h for 16-bit mode). not applicable to secondary flash. read memory sector protection status. the flash memory sector protection status is read with an instruction sequence composed of 4 oper- ations: 3 specific write operations and a read oper- ation (see table 5 or 6). the read operation will produce 01h (xx01h for 16-bit mode) if the flash sector is protected or 00h (xx00h or 16-bit mode) if the sector is not protected. internal sector select (fs0-fs7 or csboot0-csboot3) designates the flash memory sector whose protection has to be verified. alternatively, the sector protection status can also be read by the dsp accessing the flash memory protection registers in csiop space. see the sec- tion entitled flash memory sector protect for register definitions.
17/61 DSM2150F5V table 7. status bit definition note: 1. x = not guaranteed value, can be read either 1 or 0. 2. dq7-dq0 represent the data bus bits, d7-d0. 3. when the dsm2150f5 is configured for 16-bit operation, dq8-dq15 are not significant and can be ignored. reading the erase/program status bits. the device provides several status bits to be used by the dsp to confirm the completion of an erase or program cycle of flash memory. these status bits minimize the time that the dsp spends performing these tasks and are defined in table 7. the status bits can be read as many times as needed. dq8 - dq15 are insignificant and can be ignored when the dsm2150f5 is configured to operate in 16-bit mode, however, the read operation must occur on an even address boundary. for flash memory, the dsp can perform a read operation to obtain these status bits while an erase or program instruction sequence is being executed by the embedded algorithm. see the section entitled programming flash memory, on page 18, for details. data polling flag (dq7). when erasing or pro- gramming in flash memory, the data polling flag (dq7) bit outputs the complement of the bit being entered for programming/writing on the data poll- ing flag (dq7) bit. once the program instruction sequence or the write operation is completed, the true logic value is read on the data polling flag (dq7) bit. n data polling is effective after the fourth write pulse (for a program instruction sequence) or after the sixth write pulse (for an erase instruction sequence). it must be performed at the address being programmed or at an address within the flash memory sector being erased. n during an erase cycle, the data polling flag (dq7) bit outputs a 0. after completion of the cycle, the data polling flag (dq7) bit outputs the last bit programmed (it is a 1 after erasing). n if the byte/word to be programmed is in a protected flash memory sector, the instruction sequence is ignored. n if all the flash memory sectors to be erased are protected, the data polling flag (dq7) bit is reset to 0 for t timout , and then returns to the previous addressed byte. no erasure is performed. toggle flag (dq6). the device offers an alterna- tive way for determining when the flash memory program cycle is completed. during the internal write operation and when the sector select fs0- fs7 (or csboot0-csboot3) is true, the toggle flag (dq6) bit toggles from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the mem- ory. when the dsm2150f5 is configured to oper- ate in 16-bit mode, status reads must occur at even addresses, dq8 - dq15 are insignificant and can be ignored. when the internal cycle is complete, the toggling stops and the data read on the data bus is the ad- dressed memory byte/word. the device is now ac- cessible for a new read or write operation. the cycle is finished when two successive reads yield the same output data. n the toggle flag (dq6) bit is effective after the fourth write operation (for a program instruction sequence) or after the sixth write operation (for an erase instruction sequence). n if the byte/word to be programmed belongs to a protected flash memory sector, the instruction sequence is ignored. n if all the flash memory sectors selected for erasure are protected, the toggle flag (dq6) bit toggles to 0 for t timout and then returns to the previous addressed byte. error flag (dq5). during a normal program or erase cycle, the error flag (dq5) bit is to 0. this bit is set to 1 when there is a failure during flash memory byte/word program operation, sector erase, or bulk erase operation. in the case of flash memory programming, the er- ror flag (dq5) bit indicates the attempt to program a flash memory bit from the programmed state, logic 0, to the erased state, logic 1, which is not valid. the error flag (dq5) bit may also indicate a time-out condition while attempting to program a byte/word. in case of an error in a flash memory sector erase or byte/word program cycle, the flash memory sector in which the error occurred or to which the programmed byte/word belongs must no longer be used. other flash memory sectors may still be functional block fs0-fs7, or csboot0-csboot3 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 flash memory active (the desired segment is selected) data polling toggle flag error flag x erase time- out xxx
DSM2150F5V 18/61 used. the error flag (dq5) bit is reset after a re- set flash instruction sequence. erase time-out flag (dq3). the erase time- out flag (dq3) bit reflects the time-out period al- lowed between two consecutive sector erase in- struction sequence bytes/words. the erase time- out flag (dq3) bit is reset to 0 after a sector erase cycle for a time period t timout unless an additional sector erase instruction sequence is decoded. af- ter this time period, or when the additional sector erase instruction sequence is decoded, the erase time-out flag (dq3) bit is set to 1. programming flash memory when the dsm2150f5 is configured for 8-bit oper- ation, flash memory locations are programmed in 8-bit bytes to even or odd addresses. when the dsm2150f5 is configured for 16-bit op- eration, flash memory locations are programmed in 16-bit words to even addresses only. however, some dsps support the bhe (byte high enable) signal on the DSM2150F5V cntl2 input or the wrl, wrh (write low byte, write high byte) sig- nals on the cntl0 and pd3 inputs. in these cas- es, a dsp write operation can be directed to an individual byte (upper or lower) of a byte-pair. these signals do not effect read operations, only writes. reads are always by 16-bits from an even address. bhe signal on cnt2 input. see table 8. even- byte refers to locations with address a0 equal to 0, and odd byte as locations with a0 equal to 1. table 8. 16-bit data bus with bhe wrl and wrh signals on cnt0 and pd3 in- puts. see table 9. even-byte refers to locations with address a0 equal to 0, and odd byte as loca- tions with a0 equal to 1. table 9. 16-bit data bus with wrh and wrl when a byte/word of flash memory is pro- grammed, individual bits are programmed to logic 0. you cannot program a bit in flash memory to a logic 1 once it has been programmed to a logic 0. a bit must be erased to logic 1, and programmed to logic 0. that means flash memory must be erased prior to being programmed. the dsp may erase the entire flash memory array all at once or individual sector-by-sector, but not byte-by-byte (or word-by-word for 16-bit mode). however, the dsp may program flash memory byte-by-byte (or word-by-word for 16-bit mode). the flash memory requires the dsp to send an in- struction sequence to program a byte or to erase sectors (see table 5 or 6). once the dsp issues a flash memory program or erase instruction sequence, it must check for the status bits for completion. the embedded algo- rithms that are invoked inside the device provide several ways give status to the dsp. status may be checked using any of three methods: data poll- ing, data toggle, or ready/busy (pin pe4). data polling. polling on the data polling flag (dq7) bit is a method of checking whether a pro- gram or erase cycle is in progress or has complet- ed. figure 5 shows the data polling algorithm. when the dsp issues a program instruction se- quence, the embedded algorithm within the device begins. the dsp then reads the location of the byte/word to be programmed in flash memory to check status. for 16-bit operation, the status loca- tion read must be at an even address and d8-d15 can be ignored. the data polling flag (dq7) bit of this location becomes the compliment of bit 7 of the original data byte/word to be programmed. the dsp continues to poll this location, comparing the data polling flag (dq7) bit and monitoring the er- ror flag (dq5) bit. when the data polling flag (dq7) bit matches bit7 of the original data, and the error flag (dq5) bit remains 0, then the embed- ded algorithm is complete. if the error flag (dq5) bit is 1, the dsp should test the data polling flag (dq7) bit again since the data polling flag (dq7) bit may have changed simultaneously with the er- ror flag (dq5) bit (see figure 5). the error flag (dq5) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte/word or if the dsp attempted to program a 1 to a bit that was not erased (not erased is logic 0). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte/word hat was written to the flash memory with the byte/word that was intended to be written. when using the data polling method during an erase cycle, figure 5 still applies. however, the data polling flag (dq7) bit is 0 until the erase cy- cle is complete. a 1 on the error flag (dq5) bit in- dicates a time-out condition on the erase cycle, a bhe a0 d15-d8 d7-d0 0 0 odd byte even byte 0 1 odd byte 1 0 even byte wrh wrl d15-d8 d7-d0 0 0 odd byte even byte 0 1 odd byte 1 0 even byte
19/61 DSM2150F5V 0 indicates no error. the dsp can read any loca- tion (must be even address for 16-bit mode) within the sector being erased to get the data polling flag (dq7) bit and the error flag (dq5) bit. psdsoft express generates ansi c code func- tions which implement these data polling algo- rithms. figure 5. data polling flowchart plds the plds bring programmable logic to the device. after specifying the logic for the plds using psd- soft express, the logic is programmed into the de- vice and available upon power-up. the plds have selectable levels of performance and power consumption. the device contains two plds: the decode pld (dpld), and the complex pld (cpld), as shown in figure 6. the dpld performs address decoding, and gen- erates select signals for internal and external com- ponents, such as memory, registers, and i/o ports. the dpld can generate eight external chip se- lect (ecs0-ecs7) signals on port c. the cpld can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic. these logic functions can be constructed using the 16 output macrocells (omc), 24 input macrocells (imc), and the and array. table 10. dpld and cpld inputs note: 1. dsp address lines above a15 may enter the dsm device on any pin on ports a, b, c or d. see appendices for rec- ommended connections. 2. additional dsp control signals may enter the dms device on any pin on ports a, b, c, or d. see appendices for rec- ommended connections. the and array is used to form product terms. these product terms are configured from the logic definition entered in psdsoft express. a pld in- put bus consisting of 73 signals is connected to the plds. input signals are shown in table 10. turbo bit. the plds in the device can minimize power consumption by switching to standby when inputs remain unchanged for an extended time t turbo . resetting the turbo bit to 0 (bit 3 of the pmmr0 register) automatically places the plds into standby if no inputs are changing. turning the turbo mode off increases propagation delays while reducing power consumption. additionally, seven bits are available in the pmmr registers in csiop to block dsp control signals from entering the plds. this reduces power consumption and can be used only when these dsp control signals are not used in pld logic equations. each of the two plds has unique characteristics suited for its applications. they are described in the following sections. read dq5 & dq7 at valid address start read dq7 fail pass ai01369b dq7 = data yes no yes no dq5 = 1 dq7 = data yes no input source input name number of signals dsp address bus 1 a15-a0 16 dsp control signals 2 cntl2-cntl0 3 reset rst 1 porta input macrocells pa7-pa0 8 portb input macrocells pb7-pb0 8 portc input macrocells pc7-pc0 8 port d inputs pd3-pd0 4 page register pg7-pg0 8 macrocell a feedback mcella fb7-0 8 macrocell b feedback mcellb fb7-0 8 flash memory program status bit ready/busy 1
DSM2150F5V 20/61 figure 6. pld diagram decode pld (dpld) the dpld, shown in figure 7, is used for decod- ing the address for internal and external compo- nents. the dpld can be used to generate the following decode signals: n 8 main flash memory sector select ( fs0-fs7 ) signals with three product terms each n 4 secondary flash memory sector select ( csboot0-csboot3 ) signals with three product terms each n 1 internal csiop select for dsm device control and status registers ( csiop is the base address of the block of 256 byte locations) n 1 jtag select signal (enables jtag operations on port e when multiplexing jtag signals with general i/o signals) n 8 external chip select output signals for port c pins, each with one product term. pld input bus 8 input macrocell and input ports direct macrocell input to mcu data bus csiop select decode pld (dpld) page register external chip selects to port c jtag select cpld pt alloc. mcella mcellb direct macrocell access from mcu data bus 24 input macrocell (port a, b,c) 16 output macrocell i/o ports main flash memory selects 4 port d inputs to port a to port b data bus 8 8 8 1 8 1 73 16 73 24 output macrocell feedback 4 secondary flash memory selects ai05769
21/61 DSM2150F5V figure 7. dpld logic array complex pld (cpld) the cpld can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. see application note an1171 for details on how to specify logic us- ing psdsoft express. the cpld has the following blocks: n 24 input macrocells (imc) n 16 output macrocells (omc) n product term allocator n and array capable of generating up to 190 product terms n two i/o ports. each of the blocks are described in the sections that follow. the imcs and omcs are connected to the device internal data bus and can be directly accessed by the dsp. this enables the dsp software to load data into the omc or read data from both the imcs and omcs. this feature allows efficient implemen- tation of system logic and eliminates the need to connect the data bus to the and array as required in most standard pld macro cell architectures. (inputs) (24) (8) (16) (3) cntrl[2:0] (read/write control signals) i/o ports (port a, b,c) (8) pg0-pg7 (8) mcella.fb [ 7:0] (feedback) mcellb.fb [ 7:0] (feedback) a[15:0] (4) (1) pd[3:0] reset (1) rd_bsy csiop jtagsel ecs0 ecs1 8 flash main memory sector selects i/o decoder select jtag isp fs0 fs7 3 3 3 3 3 3 3 3 1 ecs2 fs1 fs2 fs3 fs6 fs5 fs4 1 1 1 1 external chip selects to port c csboot0 csboot1 csboot2 csboot3 4 secondary flash memory sector selects 3 3 3 3 ai05775 ecs3 ecs4 ecs5 ecs6 1 ecs7 1 1 1 1
DSM2150F5V 22/61 figure 8. macrocell and i/o port output macrocell (omc). eight of the omcs, mcella0-mcella7, are connected to port a pins. the other eight macrocells, mcellb0-mcellb7, are connected to ports b pins. omcs may be used for internal feedback (buried registers), or their out- puts may be routed to external port pins. the omc architecture is shown in figure 9. as shown in the figure, there are native product terms available from the and array, and borrowed prod- uct terms available (if unused) from other omc. the polarity of the product term is controlled by the xor gate. the omc can implement either se- quential logic, using the flip-flop element, or com- binatorial logic. the multiplexer selects between the sequential or combinatorial logic outputs. the multiplexer output can drive a port pin and has a feedback path to the and array inputs. the flip-flop in the omc block can be configured as a d, t, jk, or sr type in psdsoft express tm . the flip-flops clock, preset, and clear inputs may be driven from a product term of the and array. alternatively, clkin (pd1) can be used for the clock input to the flip-flop. the flip-flop is clocked on the rising edge of clkin (pd1). the preset and clear are active high inputs. each clear input can use up to two product terms. i/o ports cpld macrocells input macrocells mux mux mux mux d d q q q g d qd wr wr pdr data product term allocator dir reg. input product terms from other macrocells polarity select up to 10 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) macrocell feedback i/o port input pt input latch gate/clock mcu load pt preset mcu data in comb. /reg select pld input bus pld input bus dsp address / data bus macrocell out to mcu data load control and array cpld output i/o pin ai05770
23/61 DSM2150F5V table 11. output macrocell port and data bit assignments product term allocator. the cpld has a prod- uct term allocator. psdsoft express tm uses the product term allocator to borrow and place prod- uct terms from one macrocell to another. this hap- pens automatically in psdsoft express tm , but understanding how allocation works will help you if your logic design does not fit, in which case you may try selecting a different pin or different omc where the allocation resources may differ and the design will then fit. the following list summarizes how product terms are allocated: n mcella0-mcella7 all have three native product terms and may borrow up to six more n mcellb0-mcellb3 all have four native product terms and may borrow up to five more n mcellb4-mcellb7 all have four native product terms and may borrow up to six more. each macrocell may only borrow product terms from certain other macrocells. product terms al- ready in use by one macrocell are not available for another macrocell. product term allocation does not add any propagation delay to the logic. if an equation requires more product terms than are available to it through product term allocation, then external product terms are required, which consumes other omc. this is called product term expansion and also happens automatically in ps- dsoft express tm as needed. product tern expan- sion causes additional propagation delay because an omc is consumed by the expansion and its output is rerouted (or fed back) into the and array. you can examine the fitter report generated by psdsoft express to see resulting product term al- location and product term expansion. loading and reading the omcs. each of the two omc blocks (8 omcs each) occupies a mem- ory location in the dsp address space, as defined in the csiop block mcella0-7 and mcellb0-7 (see table 4). the flip-flops in each of the 16 omcs can be loaded from the data bus by a dsp. loading the omcs with data from the dsp takes priority over internal functions. as such, the preset, clear, and clock inputs to the flip-flop can be over- ridden by the dsp. the ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailbox- es, and handshaking protocols. data is loaded into the omc on the trailing edge of write strobe coming from cntl0. output macrocell port assignment native product terms maximum borrowed product terms data bit for loading or reading in 16-bit mode data bit for loading or reading in 8-bit mode mcella0 port a0 3 6 d0 d0 mcella1 port a1 3 6 d1 d1 mcella2 port a2 3 6 d2 d2 mcella3 port a3 3 6 d3 d3 mcella4 port a4 3 6 d4 d4 mcella5 port a5 3 6 d5 d5 mcella6 port a6 3 6 d6 d6 mcella7 port a7 3 6 d7 d7 mcellb0 port b0 4 5 d8 d0 mcellb1 port b1 4 5 d9 d1 mcellb2 port b2 4 5 d10 d2 mcellb3 port b3 4 5 d11 d3 mcellb4 port b4 4 6 d12 d4 mcellb5 port b5 4 6 d13 d5 mcellb6 port b6 4 6 d14 d6 mcellb7 port b7 4 6 d15 d7
DSM2150F5V 24/61 figure 9. cpld output macrocell the omc mask register. there is one mask register for each of the two groups of eight omcs. the mask registers can be used to block the load- ing of data to individual omcs. the default value for the mask registers is 00h, which allows load- ing of all the omcs. when a given bit in a mask register is set to a 1, the dsp is blocked from writ- ing to the associated omc. for example, suppose mcella0-3 are being used for a state machine. you would not want a dsp write to mcella to overwrite the state machine registers. therefore, you would want to load the mask register for mcella group with the value 0fh. the output enable of the omc. the omc block can be connected to an i/o port pin as a pld output. the output enable of each port pin driver is controlled by a single product term from the and array, ored with the direction register output. the pin is enabled upon power-up if no output en- able equation is defined and if the pin is declared as a pld output in psdsoft express. if the omc output is specified as an internal node and not as a port pin output in the psdsoft ex- press, then the port pin can be used for other i/o functions. the internal node feedback can be rout- ed as an input to the and array. pt allocator mask reg. pt clk pt pt pt clkin feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input macrocell i/o pin internal data bus direction register clear ( .re ) programmable ff ( d / t/jk /sr ) wr enable ( .oe ) preset ( .pr ) rd output macrocell cs ai05771
25/61 DSM2150F5V figure 10. input macrocell input macrocells (imc). the cpld has 24 imcs, one for each pin on ports a, b and c. the architecture of the imcs is shown in figure 10. the imcs are individually configurable, and can be used as a latch, a register, or to pass incoming port signals prior to driving them onto the pld in- put bus. this is useful for sampling and debounc- ing inputs to the and array (keypad inputs, etc.). additionally, the outputs of the imcs can be read by the dsp asynchronously at any time through the internal data bus using the csiop register block (see table 4). the enable for the latch and clock for the register are driven by a product term from the cpld. each product term output is used to latch or clock four imcs. port inputs 3-0 can be controlled by one product term and 7-4 by another. configurations for the imcs are specified by equa- tions specified in psdsoft express. see applica- tion note an1171 . dsp bus interface the no-glue logic dsp bus interface allows di- rect connection. dsp address, data, and control signals connect directly to the dsm device. see appendices for typical connections. dsp address, data and control signals are routed to flash memory, i/o control ( csiop ), omcs, and imcs within the dms. the dsp address range for each of these components is specified in psdsoft express tm . i/o ports there are seven programmable i/o ports: ports a, b, c, d, e, f, and g. however, typically only four of these ports are available in 8-bit dsp data con- figuration, and 3 ports with 16-bit data. each of the ports is eight bits except port d, which is 4 bits. each port pin is individually user configurable, thus allowing multiple functions per port. the ports are configured using psdsoft express tm or by the dsp writing to on-chip registers in the csiop block. the topics discussed in this section are: n general port architecture n port operating modes n csiop port registers n port data registers n individual port functionality. output macrocells bc and macrocells ab pt pt feedback and array pld input bus port driver i/o pin internal data bus direction register mux pt q q d d g latch input macrocell enable ( .oe ) d ff input macrocell _ rd ai04904c
DSM2150F5V 26/61 figure 11. general port architecture general port architecture. the general archi- tecture of the i/o port block is shown in figure 12. individual port architectures are shown in figure n to figure 14. in general, once the purpose for a port pin has been defined in psdsoft express tm , that pin is no longer available for other purposes. exceptions are noted. the ports contain an output multiplexer whose se- lect signals are driven by the configuration bits de- termined by psdsoft express. inputs to the multiplexer include the following: n output data from the data out register (for mcu i/o mode) n cpld macrocell output (omc) n external chip selects esc0-7 from the dpld to port c pins only. the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read by the dsp. the port data buffer (pdb) is connected to the internal data bus for feedback and can be read by the dsp. the data out and macrocell out- puts, direction and drive registers, and port pin input are all connected to the port data buffer (pdb). the port pins tri-state output driver enable is con- trolled by a two input or gate whose inputs come from the cpld and array enable product term and the direction register. if the enable product term of any of the array outputs are not defined and that port pin is not defined as a cpld output in psdsoft express tm , then the direction register has sole control of the buffer that drives the port pin. the contents of these registers can be altered by the dsp. the port data buffer (pdb) feedback path allows the dsp to check the contents of the registers. ports a, b, and c have imcs. the imcs can be configured as registers (for sampling or debounc- ing), as transparent latches, or direct inputs to the plds. the registers and latches are clocked by a product term from the pld and array. the out- puts from the imcs drive the pld input bus and can be read by the dsp. see the section entitled input macrocell, on page 25. internal data bus data out reg. dq dq wr wr macrocell outputs enable product term ( .oe ) ext cs read mux p d b cpld - input dir reg. input macrocell enable out data in output mux port pin data out ai05772
27/61 DSM2150F5V table 12. port operating modes note: 1. can be multiplexed with other i/o functions. 2. only in 8-bit dsp data bus configuation. port operating modes the i/o ports have several modes of operation. modes are defined using psdsoft express tm , and then runtime control from the dsp can occur using the registers in the csiop block. see application note an1171 for more detail. table 12 summarizes which modes are available on each port. each of the port operating modes are described in the following sections. mcu i/o mode. in mcu i/o mode, dsp i/o ports are expanded. the dsp can read i/o pins, set the direction of i/o pins, and change the state of i/o pins by accessing the registers in the csiop block. the csiop registers (data in, data out, and direc- tion) that implement mcu i/o mode are defined table 4 and appendix a. data in register for mcu i/o mode. the dsp may read the data in registers in the csiop block at any time to determine the logic state of a port pin. this will be the state at the pin regardless of whether it is driven by a source external to the dsm or driven internally from the dsm device. reading a logic zero for a bit in a data in register means the corresponding port pin is also at logic zero. reading logic one means the pin is logic one. each bit in a data in register corresponds to an individual port pin. for a given port, bit 0 in a data in register corresponds to pin 0 of the port. example, bit 0 of the data in register for port b cor- responds to port b pin pb0. data out register for mcu i/o mode. the dsp may write (or read) the data out register in the csiop block at any time. writing the data out reg- ister will change the logic state of a port pin only if it is not driven or controlled by the cpld. writing a logic zero to a bit in a data out register will force the corresponding port pin to be logic zero. writing logic one will drive the pin to logic one. each bit in the data out registers correspond to port pins the same way as the data in registers described above. when some pins of a port are driven by the cpld, writing to the corresponding bit in a data out register will have no effect as the cpld over- rides the data out register. direction register for mcu i/o mode. the di- rection register, in conjunction with the output en- able, controls the direction of data flow in the i/o ports. any bit set to 1 in the direction register causes the corresponding pin to be an output, and any bit set to 0 causes it to be an input. the default mode for all port pins is input. figure n shows the port architecture for ports a, b and c. the direc- tion of data flow for are controlled not only by the direction register, but also by the output enable product term from the pld and array. if the out- put enable product term is not active, the direction register has sole control of a given pins direction. drive select register. the drive select register configures the pin driver as open drain or cmos (standard push/pull) for some port pins, and con- trols the slew rate for the other port pins. an exter- nal pull-up resistor should be used for pins configured as open drain. open drain outputs are diode clamped, thus the maximum voltage on an pin configured as open drain is vcc + 0.7v. a pin can be configured as open drain if its corre- sponding bit in the drive select register is set to a 1. the default pin drive is cmos. note that the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates in a high slew rate when the corresponding bit in the drive reg- ister is set to 1. the default rate is standard slew. see appendix a for drive register bit definitions. dsp data bus. port f is used for dsp data lines d0-d7 when DSM2150F5V is configured for 8-bit operation. port g is additionally used for dsp data lines d8-d15 when configured for 16-bit operation. pld inputs. inputs from ports a, b, and c to the dpld and cpld come through imcs. inputs from port d to plds are routed directly in and do not use imcs. port mode port a port b port c port d port e port f port g mcu i/o yes yes yes yes yes no ye s 2 dsp data bus for 8-bit config dsp data bus for 16-bit config pld input though imc pld input directly mcella outputs mcellb outputs additional external cs outputs no no ye s no ye s no no no no yes no no ye s no no no ye s no no no ye s no no no ye s no no no no no no no no no no ye s ye s no no no no no no ye s no no no no no jtag isp no no no no ye s 1 no no
DSM2150F5V 28/61 pld outputs. outputs from the cpld to port a come from the omc group mcella0-7. likewise, port b is driven by mcellb0-7. outputs from the dpld to port c come from the external chip select logic block ecs0-7. jtag in-system programming (isp). some of the pins on port e implement ieee 1194.1 jtag bus for in-system programming (isp). you can multiplex the function of these port e jtag pins with other functions. see the section entitled pro- gramming in-circuit using jtag isp, and appli- cation note an1153 . enable out. the enable out register can be read by the dsp. it contains the output enable values for a given port. a logic 1 indicates the driver is in output mode. a logic 0 indicates the driver is in tri- state and the pin is in input mode. figure 12. port a, b and c structure ports a, b and c C functionality and structure ports a and b have similar functionality and struc- ture, as shown in figure 12. the two ports can be configured to perform one or more of the following functions: n mcu i/o mode n cpld output C macrocells mcella7-mcella0 can be connected to port a. mcellb7-mcellb0 can be connected to port b. n dpld output - external chip select (ecs7- ecs0) can be connected to port c. n cpld input C via the input macrocells (imc). n open drain/slew rate C pins pc7-pc0 can be configured to fast slew rate. pins pa7-pa0, pb7-pb0, and pg7-pb0 and can be configured to open drain mode. internal data bus data out register dq dq wr wr mcella7-mcella0 (port a) mcellb7-mcellb0 (port b) ext.cs (port c) enable product term ( .oe ) read mux p d b cpld - input dir register input macrocell enable out data in output mux port pin data out ai04936b
29/61 DSM2150F5V figure 13. port d structure p ort d C functionality and structure port d has four i/o pins. see figure 13. port d can be configured to perform one or more of the follow- ing functions: n mcu i/o mode n cpld input C direct input to the cpld, no input macrocells (imc) port d pins can be configured in psdsoft ex- press as input pins for other dedicated func- tions: n clkin (pd1) as input to the macrocells flip- flops and apd counter n psd chip select input (csi , pd2). driving this signal high disables the flash memory, sram and csiop. n write high-byte input (wrh , pd3) used for some 16-bit dsp connections. internal data bus data out register dq dq wr wr read mux p d b cpld - input dir register data in port d pin data out ai05774
DSM2150F5V 30/61 figure 14. port e and g structure p ort e C functionality and structure port e can be configured to perform one or more of the following functions (see figure 14): n mcu i/o mode n in-system programming (isp) C jtag port can be enabled for programming/erase of the psd device. (see the section entitled programming in-circuit using jtag isp, on page 33, for more information on jtag programming.) n open drain C pins can be configured in open drain mode p ort f C functionality and structure port f will always be connected to dsp data bus d7-d0. port g C functionality and structure port g can be configured to perform one or more of the following functions: n connected to dsp data bus d15-d8 in 16-bit configuration. n mcu i/o mode in 8-bit configuration. n open drain C pins can be configured in open drain mode in 8-bit configuration. internal data bus data out register dq dq wr wr enable product term ( .oe ) read mux p d b dir register enable out data in port pin data out ai05773
31/61 DSM2150F5V power management the device offers configurable power saving op- tions. these options may be used individually or in combinations, as follows: n all memory blocks in the device are built with zero-power technology. zero-power technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an address input, the affected memory wakes up, changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changingit happens automatically. both plds (dpld and cpld) are also zero- power, but this is not the default operation. the dsp must set a bit at run-time to achieve zero- power as described. n psd chip select input (csi , pd2) can be used to disable the internal memories and csiop registers, placing them in standby mode even if address inputs are changing. this feature does not block any internal signals or disable the plds. there is a slight penalty in memory access time when psd chip select input (csi , pd2) makes its initial transition from deselected to selected. n the pmmr registers can be written by the dsp at run-time to manage power. the device has a turbo bit in the pmmr0 register. this bit can be set to turn the turbo mode off (the default is with turbo mode turned on). while turbo mode is off, the plds can achieve standby current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is on. when the turbo mode is on, there is a significant dc current component and the ac component is higher. n further significant power savings can be achieved by blocking signals that are not used in dpld or cpld logic equations. the blocking bits in pmmr registers can be set to logic 1 by the dsp to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figure 16), so blocking unused pld inputs can significantly lower pld operating frequency and power consumption. the dsp also has the option of blocking certain pld inputs when not needed, then letting them pass for when needed for specific logic operations. table 4 and appendix a define the pmmr registers.
DSM2150F5V 32/61 power on reset, warm reset, power-down power on reset. upon power-up, the device re- quires a reset ( reset ) pulse of duration t nlnh-po after v cc is steady. during this time period, the de- vice loads internal configurations, clears some of the registers and sets the flash memory into read array mode. after the rising edge of reset ( re- set ), the device remains in the reset mode for an additional period, t opr , before the first memory ac- cess is allowed. upon power on reset, internal sector selects fs0- 7 and csboot0-7 must all be inactive and write strobe ( wr , cntl0) inactive (logic 1) for maxi- mum security of the data contents and to remove the possibility of a byte/word being written on the first edge of write strobe ( wr , cntl0). any flash memory write cycle initiation is prevented auto- matically when v cc is below v lko . warm reset. once the device is up and running, the device can be reset with a pulse of a much shorter duration, t nlnh . the same t opr period is needed before the device is operational after warm reset. figure 15 shows the timing of the power-up and warm reset. i/o pin, register and pld status at reset. ta- ble 13 shows the i/o pin, register and pld status during power on reset, warm reset and power- down mode. pld outputs are always valid during warm reset, and they are valid in power on reset once the internal device configuration bits are loaded. this loading of the device is completed typically long before the v cc ramps up to operat- ing level. once the pld is active, the state of the outputs are determined by the psdsoft express equations. figure 15. reset (reset ) timing table 13. status during power-on reset, warm reset and power-down mode port configuration power-on reset warm reset mcu i/o input mode input mode pld output valid after internal psd configuration bits are loaded (almost immediately) valid register power-on reset warm reset pmmr0 and pmmr2 cleared to 0 unchanged omc flip-flop status cleared to 0 by internal power-on reset depends on .re and .pr equations all other registers cleared to 0 cleared to 0 t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
33/61 DSM2150F5V programming in-circuit using jtag isp in-system programming (isp) can be performed through the jtag signals on port e. this serial in- terface allows programming of the entire dsm de- vice or subsections (i.e. only flash memory but not the plds) without and participation of the dsp. a blank dsm device soldered to a circuit board can be completely programmed in 15to 35 seconds. the basic jtag signals; tms, tck, tdi, and tdo form the ieee-1149.1 interface. the dsm device does not implement the ieee- 1149.1 boundary scan functions. the dsm uses the jtag interface for isp only. however, the dsm device can reside in a standard jtag chain with other jtag devices as it will remain in bypass mode while other devices perform boundary scan. isp programming time can be reduced as much as 30% by using two more signals on port e, tstat and terr in addition to tms, tck, tdi and tdo. see table 14. the flashlink tm jtag program- ming cable available from stmicroelectronics for $usd59 and psdsoft express software that is available at no charge from www.st.com/psd is all that is needed to program a dsm device using the parallel port on any pc or laptop. by default, the four pins on port c are enabled for the basic jtag signals tms, tck, tdi, and tdo on a blank device (and as shipped from factory) see application note an1153 for more details on jtag in-system programming (isp). standard jtag signals. the standard jtag signals (tms, tck, tdi, and tdo) can be en- abled by any of three different conditions that are logically ored. the following symbolic logic equation specifies the conditions enabling the four basic jtag signals (tms, tck, tdi, and tdo) on their respective port e pins. for purposes of discussion, the logic label jtag_on is used. when jtag_on is true, the four pins are enabled for jtag operation. when jtag_on is false, the four pins can be used for general device i/o as specified in psd- soft express. jtag_on can become true by any of three different ways as shown: jtag_on = 1. psdsoft express pin configuration -or- 2. psdsoft express pld equation -or- 3. dsp writes to register in csiop block method 1 is most common. this is when the jtag pins are selected in psdsoft express to be dedi- cated jtag pins. they can always transmit and receive jtag information because they are full- time jtag pins. method 2 is used only when the jtag pins are multiplexed with general i/o functions. for de- signs that need every i/o pin, the jtag pins may be used for general i/o when they are not used for isp. however, when jtag pins are multiplexed with general i/o functions, the designer must in- clude a way to get the pins back into jtag mode when it is time for jtag operations again. in this case, a single pld input from ports a, b, c, or d must be dedicated to switch the port e pins from i/ o mode back to isp mode at any time. it is recom- mended to physically connect this dedicated pld input pin to the jen\ output signal from the flashlink cable when multiplexing jtag signals. see application note an1153 for details. method 3 is rarely used to control jtag pin oper- ation. the dsp can set the port e pins to function as jtag isp by setting the jtag enable bit in a register of the csiop block, but as soon as the dsm chip is reset, the csiop block registers are cleared, which turns off the jtag-isp function. controlling jtag pins using this method is not recommended. table 14. jtag port signals jtag extensions. tstat and terr are two jtag extension signals (must be used as a pair) enabled by a command received over the four standard jtag signals (tms, tck, tdi, and tdo) by psdsoft express. they are used to speed program and erase cycles by indicating status on device pins instead of having to scan the status out serially using the standard jtag chan- nel. see application note an1153 . terr indicates if an error has occurred when erasing a sector or programming a byte in flash memory. this signal goes low (active) when an error condition occurs. tstat behaves the same as ready/busy de- scribed previously. tstat is inactive logic 1 when the device is in read mode (flash memory con- tents can be read). tstat is logic 0 when flash memory program or erase cycles are in progress. tstat and terr can be configured as open- drain type signals with psdsoft express. this fa- cilitates a wired-or connection of tstat signals from multiple DSM2150F5V devices and a wired- or connection of terr signals from those same port e pin jtag signals description pe0 tms mode select pe1 tck clock pe2 tdi serial data in pe3 tdo serial data out pe4 tstat status pe5 terr error flag
DSM2150F5V 34/61 devices. this is useful when several devices are chained together in a jtag environment. psd- soft express puts tstat and terr signals to open-drain by default. click on 'properties' in the jtag-isp window of psdsoft express to change to standard cmos push-pull. it is recommended to use 10 k w pull-up resistors to v cc on all jtag- isp signals on your circuit board. initial delivery state when delivered from st, the device has all bits in the memory and plds erased to logic 1. the dsm configuration register bits are set to 0. the code, configuration, and pld logic are loaded using the programming procedure. the four basic jtag isp signals (tck, tms, tdi, tdo) are ready for isp function.
35/61 DSM2150F5V ac/dc parameters these tables describe the ac and dc parameters of the device: o dc electrical specification o ac timing specification n pld timing C combinatorial timing C synchronous clock mode C asynchronous clock mode C input microcell timing n dsp timing C read timing Cwrite timing C reset timing the following are issues concerning the parame- ters presented: n in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the device is in each mode. also, the supply power is considerably different if the turbo bit is 0. n the ac power component gives the pld and flash memory a ma/mhz specification. figure 16 shows the pld ma/mhz as a function of the number of product terms (pt) used. n the fitter report of psdsoft express indicates the number of product terms (pts) used for a given design. this number may be used to estimate pld power consumption using figure 16. n in the pld timing parameters, add the required delay when turbo bit is 0. figure 16. pld i cc /frequency consumption (3.3 v) 0 10 20 30 40 50 60 v cc = 3v 01015 5 20 25 i cc C (ma) turbo on (100%) turbo on (25%) turbo off turbo off highest composite frequency at pld inputs (mhz) pt 100% pt 25% ai03100
DSM2150F5V 36/61 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 15. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) symbol parameter min. max. unit t stg storage temperature C65 125 c t lead lead temperature during soldering (20 seconds max.) 1 235 c v io input and output voltage (q = v oh or hi-z) C0.6 4.0 v v cc supply voltage C0.6 4.0 v v pp device programmer supply voltage C0.6 14.0 v v esd electrostatic discharge voltage (human body model) 2 C2000 2000 v
37/61 DSM2150F5V dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 16. operating conditions table 17. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. figure 17. ac measurement i/o waveform figure 18. ac measurement load circuit table 18. capacitance note: 1. sampled only, not 100% tested. 2. typical values are for t a = 25c and nominal supply voltages. symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v t a ambient operating temperature (industrial) C40 85 c symbol parameter min. max. unit c l load capacitance 30 pf 0.9v cc 0v test point 1.5v ai04947 device under test 2.0 v 400 w c l = 30 pf (including scope and jig capacitance) ai04948 symbol parameter test condition typ . 2 max . unit c in input capacitance (for input pins) v in = 0v 46 pf c out output capacitance (for input/ output pins) v out = 0v 812 pf c vpp capacitance (for cntl2/v pp )v pp = 0v 18 25 pf
DSM2150F5V 38/61 table 19. ac symbols for pld timing example: t avwl C time from address valid to write input low. figure 19. switching waveforms C key signal letters signal behavior a address input t time c ceout output l logic level low d input data h logic level high e e input v valid n reset input or output x no longer a valid logic level p port signal output z float q output data pw pulse width rrd input (read) s chip select input, bms , dms , ioms , or fsx wwr input (write) b v stby output m output macrocell waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state ai03102
39/61 DSM2150F5V table 20. dc characteristics note: 1. reset has hysteresis. v il1 is valid at or below 0.2v cc C0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected (csi >v cc C0.3 v) or the dsp is not changing state of any address signal. 3. pld is in non-turbo mode, and none of the pld inputs are switching. 4. no inputs floating, must be solid logic 1 or 0 (pullup to vcc or gnd, or actively driven) 5. see figure 16 for the pld current calculation. 6. i out = 0 ma, meaning outputs are driving no loads. symbol parameter conditions min. typ. max. unit v ih high level input voltage 3.0 v < v cc < 3.6 v 0.7v cc v cc +0.5 v v il low level input voltage 3.0 v < v cc < 3.6 v C0.5 0.8 v v ih1 reset high level input voltage (note 1 ) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (note 1 ) C0.5 0.2v cc C0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 1.5 2.2 v v ol output low voltage i ol = 20 a, v cc = 3.0v 0.01 0.1 v i ol = 4 ma, v cc = 3.0 v 0.15 0.45 v v oh output high voltage i oh = C20 a, v cc = 3.0 v 2.9 2.99 v i oh = C1 ma, v cc = 3.0 v 2.7 2.8 v i stby stand-by supply current csi >v cc C0.3 v (note 2,3,4 ) 50 100 a i li input leakage current v ss < v in < v cc C1 .1 1 a i lo output leakage current 0.45 < v in < v cc C10 5 10 a i cc (dc) (note 6 ) operating supply current pld only pld_turbo = off, f = 0 mhz (note 3 ) 0 a/pt pld_turbo = on, f = 0 mhz 200 400 a/pt flash memory during flash memory write/ erase only 10 25 ma read only, f = 0 mhz 0 0 ma i cc (ac) pld ac adder (see note 5 ) flash memory ac adder 1.5 2.0 ma/ mhz
DSM2150F5V 40/61 table 21. cpld combinatorial timing note: 1. fast slew rate output available on port c and port f. table 22. cpld microcell synchronous clock mode timing note: 1. fast slew rate output available on port c and port f. 2. clkin (pd1) t clcl = t ch + t cl . symbol parameter conditions -12 pt aloc turbo off slew rate 1 unit min max t pd cpld input pin/feedback to cpld combinatorial output 43 add 4 add 20 sub 6 ns t ea cpld input to cpld output enable 45 add 20 sub 6 ns t er cpld input to cpld output disable 45 add 20 sub 6 ns t arp cpld register clear or preset delay 43 add 20 sub 6 ns t arpw cpld register clear or preset pulse width 30 add 20 ns t ard cpld array delay any microcell 27 add 4 ns t turbo minimum time between switching of any pld inputs which prevents pld from entering standby mode. pld inputs that switch less frequently than this parameter allow standby pld mode. 100 ns symbol parameter conditions -12 pt aloc turbo off slew rate 1 unit min max f max maximum frequency external feedback 1/(t s +t co ) 20.4 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co C10) 25.6 mhz maximum frequency pipelined data 1/(t ch +t cl ) 35.7 mhz t s input setup time 23 add 4 add 20 ns t h input hold time 0 ns t ch clock high time clock input 14 ns t cl clock low time clock input 14 ns t co clock to output delay clock input 26 sub 6 ns t ard cpld array delay any microcell 27 add 4 ns t min minimum clock period 2 t ch +t cl 28 ns
41/61 DSM2150F5V table 23. cpld microcell asynchronous clock mode timing figure 20. input to output disable / enable figure 21. asynchronous reset / preset symbol parameter conditions -12 pt aloc turbo off slew rate unit min max f maxa maximum frequency external feedback 1/(t sa +t coa ) 20.8 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa C10) 26.3 mhz maximum frequency pipelined data 1/(t cha +t cla ) 30.3 mhz t sa input setup time 10 add 4 add 20 ns t ha input hold time 12 ns t cha clock high time 18 add 20 ns t cla clock low time 15 add 20 ns t coa clock to output delay 38 add 20 sub 6 ns t ard cpld array delay any microcell 27 add 4 ns t mina minimum clock period 1/f cnta 38 ns ter tea input input to output enable/disable ai02863 tarp register output tarpw reset/preset input ai02864
DSM2150F5V 42/61 figure 22. synchronous clock mode timing C pld figure 23. asynchronous clock mode timing (product term clock) table 24. input microcell timing note: 1. inputs from port a, b, and c relative to register/latch clock from the pld. figure 24. input microcell timing (product term clock) symbol parameter conditions -12 pt aloc turbo off unit min max t is input setup time (note 1 ) 0ns t ih input hold time (note 1 ) 23 add 20 ns t inh nib input high time (note 1 ) 13 ns t inl nib input low time (note 1 ) 13 ns t ino nib input to combinatorial delay (note 1 ) 62 add 4 add 20 ns t ch t cl t co t h t s clkin input registered output tcha tcla tcoa tha tsa clock input registered output ai02859 t inh t inl t ino t ih t is pt clock input output ai03101
43/61 DSM2150F5V table 25. read timing note: 1. any input used to select an internal dsm function. figure 25. read timing symbol parameter conditions -12 turbo off unit min max t avqv address valid to data valid (note 1 ) 120 add 20 ns t slqv cs valid to data valid 120 ns t rlqv rd to data valid 8-bit bus 35 ns t rhqx rd data hold time 1 ns t rlrh rd pulse width 40 ns t rhqz rd to data high-z 20 ns t avqv t slqv t rlqv t rhqx trhqz t rlrh address valid data valid address non-multiplexed bus data non-multiplexed bus csi rd ai04908
DSM2150F5V 44/61 table 26. write timing note: 1. any input used to select an internal psm function. 2. assuming data is stable before active write signal. 3. assuming write is active before data becomes valid. 4. twhax2 is the address hold time for dpld inputs that are used to generate sector select signals for internal dsm memory. 5. twhax_16 is 11 ns when writing to the output microcells figure 26. write timing symbol parameter conditions -12 unit min max t avwl address valid to leading edge of wr (note 1 ) 8ns t slwl cs valid to leading edge of wr 8ns t dvwh wr data setup time 45 ns t whdx_8 wr data hold time for 8-bit mode 5 ns t whdx_16 wr data hold time for 16-bit mode (note 5) 8 ns t wlwh wr pulse width 45 ns t whax1 trailing edge of wr to address invalid 1.75 ns t whax2 trailing edge of wr to dpld address invalid (note 4 ) 0ns t whpv trailing edge of wr to port output valid using i/o port data register 33 ns t dvmv data valid to port output valid using microcell register preset/clear (note 3 ) 68 ns t wlmv wr valid to port output valid using microcell register preset/clear (note 2 ) 70 ns t avwl t slwl t whdx t whax t wlwh t dvwh address valid data valid address non-multiplexed bus data non-multiplexed bus csi wr ai04909
45/61 DSM2150F5V table 27. flash memory program, write and erase times note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid tq7vqv time units before the data byte, dq0-dq7, is valid for reading. figure 27. reset (reset ) timing table 28. reset (reset ) timing note: 1. reset (reset ) does not reset flash memory program or erase cycles. 2. warm reset aborts flash memory program or erase cycles, and puts the device in read mode. symbol parameter min. typ. max. unit flash bulk erase 1 (pre-programmed) 330s flash bulk erase (not pre-programmed) 10 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 1200 s program / erase cycles (per sector) 100,000 cycles t timeout sector erase time-out 80 s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) 2 30 ns t timout toggle flag toggles after suspend sector erase instruction 0.1 15 s t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset symbol parameter conditions min max unit t nlnh reset active low time 1 300 ns t nlnhCpo power on reset active low time 1 ms t nlnhCa warm reset active low time 2 25 us t opr reset high to operational device 300 ns t read_array flash memory returns to read mode after flash reset intruction if flash program, erase, or error condition was in progress 25 us
DSM2150F5V 46/61 table 29. isc timing note: 1. for non-pld programming, erase or in by-pass mode. 2. for program or erase pld only. figure 28. isc timing symbol parameter conditions -12 unit min max t isccf clock (tck, pc1) frequency (except for pld) (note 1 ) 12 mhz t iscch clock (tck, pc1) high time (except for pld) (note 1 ) 40 ns t isccl clock (tck, pc1) low time (except for pld) (note 1 ) 40 ns t isccfp clock (tck, pc1) frequency (pld only) (note 2 ) 2 mhz t iscchp clock (tck, pc1) high time (pld only) (note 2 ) 240 ns t iscclp clock (tck, pc1) low time (pld only) (note 2 ) 240 ns t iscpsu isc port set up time 12 ns t iscph isc port hold up time 5 ns t iscpco isc port clock to output 32 ns t iscpzv isc port high-impedance to valid output 32 ns t iscpvz isc port valid output to high-impedance 32 ns iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscph t iscpsu t iscpvz t iscpzv t iscpco t ai02865
47/61 DSM2150F5V package mechanical tqfp80 - 80 lead plastic quad flatpack note: drawing is not to scale. tqfp80 - 80 lead plastic quad flatpack symb. mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.950 1.050 0.0374 0.0413 a 3.5 0.0 7.0 3.5 0.0 7.0 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.090 0.200 0.0035 0.0079 d 14.000 0.5512 d1 12.000 0.4724 d2 9.500 0.3740 e 14.000 0.5512 e1 12.000 0.4724 e2 9.500 0.3740 e 0.500 0.0197 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 cp 0.080 0.0031 n80 80 nd 20 20 ne 20 20 qfp-a nd e1 cp b e a2 a n l a1 a d1 d 1 e ne c d2 e2 l1
DSM2150F5V 48/61 table 30. pin assignments C tqfp80 pin no. pin assign ments pin no. pin assign ments pin no. pin assign ments pin no. pin assign ments 1 pd2 21 pg0 41 pc0 61 pb0 2 pd3 22 pg1 42 pc1 62 pb1 3 ad0 23 pg2 43 pc2 63 pb2 4 ad1 24 pg3 44 pc3 64 pb3 5 ad2 25 pg4 45 pc4 65 pb4 6 ad3 26 pg5 46 pc5 66 pb5 7 ad4 27 pg6 47 pc6 67 pb6 8 gnd 28 pg7 48 pc7 68 pb7 9 v cc 29 v cc 49 gnd 69 v cc 10 ad5 30 gnd 50 gnd 70 gnd 11 ad6 31 pf0 51 pa0 71 pe0 12 ad7 32 pf1 52 pa1 72 pe1 13 ad8 33 pf2 53 pa2 73 pe2 14 ad9 34 pf3 54 pa3 74 pe3 15 ad10 35 pf4 55 pa4 75 pe4 16 ad11 36 pf5 56 pa5 76 pe5 17 ad12 37 pf6 57 pa6 77 pe6 18 ad13 38 pf7 58 pa7 78 pe7 19 ad14 39 reset 59 cntl0 79 pd0 20 ad15 40 cntl2 60 cntl1 80 pd1
49/61 DSM2150F5V part numbering table 31. ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. example: dsm21 50 f5 v - 12 t 6 device type dsm21=dsp system memory for adsp-21xxx famly dsm series 50 = 4.25m bit, dual array flash, 40 i/o main flash memory density f5 = 4mbit operating voltage (vcc) v = 3.3v 10% access time 12 = 120 nsec package t = 80-pin tqfp temperature range 6 = C40 to 85 o c (industrial)
DSM2150F5V 50/61 appendix a. csiop register bit definitions table 32. data-in registers C ports a, b, c, d, e, g note: bit definitions (read-only registers): read port pin status when port is in mcu i/o input mode. table 33. data-out registers C ports a, b, c, d, e, g note: bit definitions: latched data for output to port pin when pin is configured in mcu i/o output mode. table 34. direction registers C ports a, b, c, d, e, g note: bit definitions: port pin 0 = port pin is configured in input mode (default). port pin 1 = port pin is configured in output mode. table 35. drive registers C ports a, b, e, g note: bit definitions: port pin 0 = port pin is configured for cmos output driver (default). port pin 1 = port pin is configured for open drain output driver. table 36. drive registers C port c note: bit definitions: port pin 0 = port pin is configured for cmos output driver (default). port pin 1 = port pin is configured in slew rate mode. table 37. enable-out registers C ports a, b, c note: bit definitions (read-only registers): port pin 0 = port pin is in tri-state driver (default). port pin 1 = port pin is enabled. table 38. input macrocells C ports a, b, c note: bit definitions (read-only registers): read input macrocell (imc7-imc0) status on ports a, b and c. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 imcell 7 imcell 6 imcell 5 imcell 4 imcell 3 imcell 2 imcell 1 imcell 0
51/61 DSM2150F5V table 39. output macrocells a register note: bit definitions: write register: load mcella7-mcella0 with 0 or 1. read register: read mcella7-mcella0 output status. table 40. output macrocells b register note: bit definitions: write register: load mcellb7-mcellb0 with 0 or 1. read register: read mcellb7-mcellb0 output status. table 41. mask macrocells a register note: bit definitions: mcella_prot 0 = allow mcella flip-flop to be loaded by mcu (default). mcella_prot 1 = prevent mcella flip-flop from being loaded by dsp. table 42. mask macrocells b register note: bit definitions: mcellb_prot 0 = allow mcellb flip-flop to be loaded by mcu (default). mcellb_prot 1 = prevent mcellb flip-flop from being loaded by dsp. table 43. flash memory protection register note: bit definitions (read-only register): sec_prot 1 = primary flash memory sector is write protected. sec_prot 0 = primary flash memory sector is not write protected. table 44. flash boot protection register note: bit definitions: sec_prot 1 = secondary flash memory sector is write protected. sec_prot 0 = secondary flash memory sector is not write protected. security_bit 0 = security bit in device has not been set. security_bit 1 = security bit in device has been set. table 45. jtag enable register note: bit definitions: jtagenable 1 = jtag port is enabled. jtagenable 0 = jtag port is disabled. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcella 7 mcella 6 mcella 5 mcella 4 mcella 3 mcella 2 mcella 1 mcella 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcellb 7 mcellb 6 mcellb 5 mcellb 4 mcellb 3 mcellb 2 mcellb 1 mcellb 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcella 7 mcella 6 mcella 5 mcella 4 mcella 3 mcella 2 mcella 1 mcella 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcellb 7 mcellb 6 mcellb 5 mcellb 4 mcellb 3 mcellb 2 mcellb 1 mcellb 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 security_bit not used not used not used sec3_prot sec2_prot sec1_prot sec0_prot bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used not used not used not used not used not used not used jtagenable
DSM2150F5V 52/61 table 46. page register note: bit definitions: configure page input to pld. default is pgr7-pgr0=0. table 47. pmmr0 register note: the bits of this register are cleared to zero following power-up. subsequent reset (reset ) pulses do not clear the registers. note: bit definitions: pld turbo 0 = pld turbo is on. 1 = pld turbo is off, saving power. pld array clk 0 = clkin to the pld and array is connected. every clkin change powers up the pld when turbo bit is off. 1 = clkin to the pld and array is disconnected, saving power. pld mcells clk 0 = clkin to the pld macrocells is connected. 1 = clkin to the pld macrocells is disconnected, saving power. table 48. pmmr2 register note: for bit 4, bit 3, bit 2: see table 47 for the signals that are blocked on pins cntl0-cntl2. note: bit definitions: pld array addr 0 = address a7-a0 are connected to the pld array. 1 = address a7-a0 are blocked from the pld array, saving power. pld array cntl2 0 = cntl2 input to the pld and array is connected. every clkin change powers up the pld when turbo bit is off. 1 = cntl2 input to the pld and array is disconnected, saving power. pld array cntl1 0 = cntl1 input to the pld and array is connected. every clkin change powers up the pld when turbo bit is off. 1 = cntl1 input to the pld and array is disconnected, saving power. pld array cntl0 0 = cntl0 input to the pld and array is connected. every clkin change powers up the pld when turbo bit is off. 1 = cntl0 input to the pld and array is disconnected, saving power. pld array wrh 0 = wrh input to the pld and array is connected. 1 = wrh input to the pld and array is disconnected, saving power. table 49. memory_id0 register note: bit definitions: f_size[3:0] 5h = primary flash memory size is 4 mbit 6 h = primary flash memory size is 8 mbit table 50. memory_id1 register note: bit definitions: b_size[3:0] 2h = secondary nvm size is 256 kbit 3 h = secondary nvm size is 512 kbit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pgr 7 pgr 6 pgr 5 pgr 4 pgr 3 pgr 2 pgr 1 pgr 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used (set to 0) not used (set to 0) pld mcells clk pld array clk pld turbo not used (set to 0) not used (set to 0) not used (set to 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used (set to 0) pld array wrh not used (set to 0) pld array cntl2 pld array cntl1 pld array cntl0 not used (set to 0) pld array addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used (set to 0) not used (set to 0) not used (set to 0) not used (set to 0) f_size 3 f_size 2 f_size 1 f_size 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used (set to 0) not used (set to 0) not used (set to 0) not used (set to 0) b_size 3 b_size 2 b_size 1 b_size 0
53/61 DSM2150F5V appendix b. typical connections, DSM2150F5V and adsp-21535 blackfin dsp figure 29. typical connections, DSM2150F5V and adsp-21535 blackfin dsp adsp-21535 blackfin clkin1 addr18 addr16 _reset sport0 serial device serial device i/o osc clock out clkout data7-data0 byte select 1 _aoe _abe1 _ams0 _ams1 _awe write read spi0 spi serial device uart1 uart device pwm/timer/ capture pc1 pc2 pc0 _reset DSM2150F5V pf7-pf0 cntl0 (_wr) cntl1 (_rd) cntl2 (_bhe) addr17 addr16 addr17 addr18 _reset pc6 mem select 0 _ams2 tmr2-0 bmode0 bmode1 bmode2 pll bypass bypass pa3 pa2 pa1 pa0 pa7 pa6 pa5 pa4 pld & i/o gpio/intr/ spi sel pf15-0 interrupt nmi spi1 spi serial device uart0 (irda) uart device 16 6 6 3 3 2 2 3 usb device(s) usb 8 pci bus pci 54 sdram sync mem xtali rtc xtal 32.768khz xtalo pg7-pg0 data15-data8 addr21 addr19 pc4 pc5 pc3 addr20 addr19 addr20 addr21 addr2 addr0 a1 a2 a0 addr1 _abe0 (addr0) _abe3 (addr1) addr2 addr5 addr3 a4 a5 a3 addr4 addr3 addr4 addr5 _ams3 _abe2 _are addr8 addr6 a7 a8 a6 addr7 addr6 addr7 addr8 addr11 addr9 a10 a11 a9 addr10 addr9 addr10 addr11 addr14 addr12 a13 a14 a12 addr13 addr12 addr13 addr14 addr15 a15 addr15 sleep pd2 (_csi) sleep pb3 pb2 pb1 pb0 pb7 pb6 pb5 pb4 pe4 pe1 pe0 pe3 pe2 pe6 i/o pe7 i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pc7 i/o pd0 pd3 pd1 pe5 i/o i/o i/o i/o i/o no connect 512k byte x 16 flash mem 32k byte x 16 flash mem 16 cell pld 8 data 8 data ardy tdo tdi tck tms _trst _emu sport1 dsm jtag connector tms tck tdi tdo _reset vcc tms tck tdi tdo optional tstat optional _terr 10k jtag tms jtag tck jtag tdi jtag tdo jtag _trst emulator status 33 dsp jtag connector optionally combine jtag connectors and chain devices 33
DSM2150F5V 54/61 typical memory map, DSM2150F5V and adsp21535 blackfin dsp there many different ways to place (or map) the addresses of dsm memory and i/o depending on system requirements. the dpld allows complete mapping flexibility. figure 30 shows one possible system memory map. in this example, the dsp will bypass its internal boot rom at power-on and begin executing code directly from the DSM2150F5V secondary flash memory. while executing this code, the dsp will load the contents of the DSM2150F5V main flash memory into the adsp-21535 internal sram, then execute code from that high performance sram. the advantage of this is speed, flexibility, iap, clean software partitioning, and parameter stor- age. C loading external flash memory to internal sram by 16-bits is faster than booting by 8- bits. also, subsequent loading of new memo- ry overlays during runtime is also faster by 16-bits. C bypassing internal dsp boot rom and exe- cuting from dsm secondary memory pro- vides total flexibility to meet system requirements. like having custom boot rom programmable by jtag. C in-application programming (iap) can be im- plemented by placing custom loader code in dsm secondary flash which, when executed, allows the dsp to receive data over any com- munication channel (i.e. usb) and write new code/data the dsm main flash memory. since the dsm flash arrays are independent, it is possible to read from the secondary flash while writing to the main flash. C since the dsm secondary flash has smaller sector sizes, small data sets and calibration constants may be stored there. eeprom emulation techniques can be used. C placing start-up and iap code in dsm sec- ondary flash keeps it totally separate dsm main flash memory, affording clean software partitioning. this also ensures robust system operaton since start-up code will always be there and removed from accitental writes or erasures of dsm main flash. the nomenclature fs0..fs7 in figure 30 are desig- nators for the individual sectors of main flash memory, 64 kbytes each. csboot0..csboot3 are designators for the individual secondary flash memory segments, 8 kbytes each. csiop desig- nates the dsm control register block. the designer may easily specify memory mapping in a point-and-click software environment using psdsoft express tm . figure 30. memory map, adsp-21535 30000 3ffff 40000 4ffff 5ffff 6ffff 7ffff 8ffff 9ffff 50000 60000 70000 80000 90000 2ffff 20000 fs0 64k bytes main flash fs1 64k bytes main flash fs7 64k bytes main flash fs6 64k bytes main flash fs5 64k bytes main flash fs4 64k bytes main flash fs3 64k bytes main flash fs2 64k bytes main flash csboot , 8kb 2nd flash csboot , 8kb 2nd flash csboot , 8kb 2nd flash csboot , 8kb 2nd flash 00000-01fff 02000-03fff 04000-05fff 06000-07fff csiop , control regs 10000-100ff nothing mapped nothing mapped
55/61 DSM2150F5V specifying the memory map with psdsoft express tm the memory map shown in figure 30 can be eas- ily implemented using psdsoft express tm in a point-and-click environment. psdsoft express tm will generate hardware definition language (hdl) statements of the abel language. figure 31 shows the resulting equations generated by psdsoft express tm . figure 31. hdl statements generated from psdsoft express to implement memory map specifying these equations using psdsoft ex- press tm is very simple. figure 32 shows how to specify the equation for the 64 kbyte flash mem- ory segment, fs0 . notice fs0 is qualified with the signal ams0 . this specification process is repeat- ed for all other flash memory segments, the csiop register block, and any external chip select signals that may be needed. figure 32. psdsoft express tm memory mapping csiop = ((address >= ^h10000) & (address <= ^h100ff) & (!_ams0)); fs0 = ((address >= ^h20000) & (address <= ^h2ffff) & (!_ams0)); fs1 = ((address >= ^h30000) & (address <= ^h3ffff) & (!_ams0)); fs2 = ((address >= ^h40000) & (address <= ^h4ffff) & (!_ams0)); fs3 = ((address >= ^h50000) & (address <= ^h5ffff) & (!_ams0)); fs4 = ((address >= ^h60000) & (address <= ^h6ffff) & (!_ams0)); fs5 = ((address >= ^h70000) & (address <= ^h7ffff) & (!_ams0)); fs6 = ((address >= ^h80000) & (address <= ^h8ffff) & (!_ams0)); fs7 = ((address >= ^h90000) & (address <= ^h9ffff) & (!_ams0)); csboot0 = ((address >= ^h0000) & (address <= ^h1fff) & (!_ams0)); csboot1 = ((address >= ^h2000) & (address <= ^h3fff) & (!_ams0)); csboot2 = ((address >= ^h4000) & (address <= ^h5fff) & (!_ams0)); csboot3 = ((address >= ^h6000) & (address <= ^h7fff) & (!_ams0));
DSM2150F5V 56/61 appendix c. typical connections, DSM2150F5V and adsp-21062 sharc dsp figure 33. typical connections, DSM2150F5V and adsp-21062 sharc dsp adsp-21062l sharc dsp clocks addr18 addr16 _reset timer out timexp data23-data16 pc1 pc2 pc0 _reset DSM2150F5V pf7-pf0 addr17 addr16 addr17 addr18 _reset tdo tdi tck tms _trst _emu gpio flag3-0 4 host host interface serial device sport0 addr21 addr19 pc4 pc5 pc3 addr20 addr19 addr20 addr21 addr2 addr0 a1 a2 a0 addr1 addr0 addr1 addr2 addr5 addr3 a4 a5 a3 addr4 addr3 addr4 addr5 addr8 addr6 a7 a8 a6 addr7 addr6 addr7 addr8 addr11 addr9 a10 a11 a9 addr10 addr9 addr10 addr11 addr14 addr12 a13 a14 a12 addr13 addr12 addr13 addr14 addr15 a15 addr15 pe4 pe1 pe0 pe3 pe2 pe6 i/o pe7 i/o pd0 i/o pd1 pd3 pd2 pe5 i/o i/o i/o i/o i/o 512k byte x 8 flash mem 32k byte x 8 flash mem 16 cell pld 8 data pg3 pg2 pg1 pg0 pg7 pg6 pg5 pg4 i/o i/o i/o i/o i/o i/o i/o i/o boot mem select _rd _bms _wrh _ms3-0 _wr write read cntl0 (_wr) cntl1 (_rd) cntl2 ack peripheral link port 3 6 peripheral link port 0 6 peripheral link port 1 6 peripheral link port 2 6 clock circuitry interrupt sources irq2-0 3 peripheral dma control data47-data8 addr31-addr22 dsm jtag connector tms tck tdi tdo _reset vcc tms tck tdi tdo optional tstat optional _terr 10k jtag tms jtag tck jtag tdi jtag tdo jtag _trst emulator status 33 dsp jtag connector optionally combine jtag connectors and chain devices 33 serial device sport1 peripheral link port 5 6 peripheral link port 4 6 6 6 eboot lboot pa3 pa2 pa1 pa0 pa7 pa6 pa5 pa4 pld & i/o pb3 pb2 pb1 pb0 pb7 pb6 pb5 pb4 pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pc7 pc6 pld & i/o pld & i/o pd3 pd2 pd1 pd0 i/o i/o i/o i/o sharc
57/61 DSM2150F5V appendix d. typical connections, DSM2150F5V and adsp-ts101s tigersharc dsp figure 34. typical connections for adsp-ts101s tigersharc dsp adsp-ts101s tigersharc clocks addr18 addr16 _reset timer out _tmroe data7-data0 pc1 pc2 pc0 _reset DSM2150F5V pf7-pf0 addr17 addr16 addr17 addr18 _reset tdo tdi tck tms _trst _emu gpio flag3-0 4 host host interface sdram sync mem addr21 addr19 pc4 pc5 pc3 addr20 addr19 addr20 addr21 addr2 addr0 a1 a2 a0 addr1 addr0 addr1 addr2 addr5 addr3 a4 a5 a3 addr4 addr3 addr4 addr5 addr8 addr6 a7 a8 a6 addr7 addr6 addr7 addr8 addr11 addr9 a10 a11 a9 addr10 addr9 addr10 addr11 addr14 addr12 a13 a14 a12 addr13 addr12 addr13 addr14 addr15 a15 addr15 pe4 pe1 pe0 pe3 pe2 pe6 i/o pe7 i/o pd0 i/o pd1 pd3 pd2 pe5 i/o i/o i/o i/o i/o 512k byte x 8 flash mem 32k byte x 8 flash mem 16 cell pld 8 data pg3 pg2 pg1 pg0 pg7 pg6 pg5 pg4 i/o i/o i/o i/o i/o i/o i/o i/o pc7 pc6 pld & i/o pld & i/o boot mem select _rd _bms _wrh _ms0 _wrl write low byte read cntl0 (_wr) cntl1 (_rd) cntl2 _ms1 peripheral link port 3 11 peripheral link port 0 11 peripheral link port 1 11 peripheral link port 2 11 clock circuitry interrupt sources _intr3-0 4 peripheral dma control data63-data8 addr31-addr22 dsm jtag connector tms tck tdi tdo _reset vcc tms tck tdi tdo optional tstat optional _terr 10k jtag tms jtag tck jtag tdi jtag tdo jtag _trst emulator status 33 dsp jtag connector optionally combine jtag connectors and chain devices 33 eboot pa3 pa2 pa1 pa0 pa7 pa6 pa5 pa4 pld & i/o pb3 pb2 pb1 pb0 pb7 pb6 pb5 pb4 pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pd3 pd2 pd1 pd0 i/o i/o i/o i/o
DSM2150F5V 58/61 appendix e. typical connections, DSM2150F5V and adsp-2191 note: dsp hclk is limited to 45 mhz to satisfy DSM2150F5V parameter, t avwl . if hclk is great- er than 45 mhz, a non-inverting buffer should be placed between wr signal output from adsp- 219x and cntl0 input to dsm2150. this delays the falling edge of wr to satisfy t avwl , however, the write hold enable (e_whe) memory space setting of the adsp-2191 must be set to hold the dsp address after the delayed rising edge of wr . figure 35. typical connections, DSM2150F5V and adsp-2191m adsp-2191m a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 clkin xtal addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 a12 a13 a14 a15 addr12 addr13 addr14 addr15 a18 addr16 _reset sport0 serial chn serial device sport1 serial chn serial device pf0 pf1 pf2 pf8 pf9 pf6 pf10 pf7 pf3 pf4 pf5 i/o clock or xtal _br _bg _bgh bus_request grant_hung bus_grant clock out clkout i/o i/o i/o i/o i/o i/o boot mem select _rd _bms _ioms _msx _wr write read i/o i/o i/o i/o i/o pf11 pf12 pf13 pf14 pf15 i/o i/o i/o i/o sport2 serial or (2) spi serial spi device rxd, txd uart device timer/ capture addr17 a16 a17 addr18 reset i/o mem select ack host port hx tmr2-0 bmode0 bmode1 opmode pll bypass bypass data7-data0 8 data pc5 pc6 pc4 _reset DSM2150F5V pf7-pf0 a1 a2 a0 a4 a5 a3 a7 a8 a6 a10 a11 a9 a13 a14 a12 a15 pe4 pe1 pe0 pe3 pe2 pe6 i/o pe7 i/o pd3 pd2 pe5 i/o i/o i/o i/o 512k byte x 8 flash mem 32k byte x 8 flash mem 16 cell pld pg3 pg2 pg1 pg0 pg7 pg6 pg5 pg4 i/o i/o i/o i/o i/o i/o i/o i/o cntl0 (_wr) cntl1 (_rd) cntl2 dsm jtag connector tms tck tdi tdo _reset vcc tms tck tdi tdo optional tstat optional _terr 10k jtag tms jtag tck jtag tdi jtag tdo jtag _trst emulator status 33 dsp jtag connector optionally combine jtag connectors and chain devices 33 pa3 pa2 pa1 pa0 pa7 pa6 pa5 pa4 pld & i/o pb3 pb2 pb1 pb0 pb7 pb6 pb5 pb4 pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pc1 pc0 pld & i/o pld & i/o pd1 pd0 pc3 pc2 pld & i/o pld & i/o tdo tdi tck tms _trst _emu mem select a19 addr19 pc7
59/61 DSM2150F5V appendix f. typical connections, DSM2150F5V and adsp-2188m figure 36. typical connections, DSM2150F5V and adsp-2188m adsp-2188m a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 clkin xtal addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 a12 a13 d16 d17 addr12 addr13 addr14 addr15 d18 d19 addr16 addr17 pwdack power down _reset _reset sport0 serial chn serial device sport1 serial chn serial device fl0 fl1 fl2 _irql0/pf5 _irql1/pf6 pf3 _irq2/pf7 _irqe/pf4 pf0/modea pf1/modeb pf2/mocec i/o intr/i_o intr/i_o intr/i_o intr/i_o clock or xtal _br _bg _bgh bus_request grant_hung bus_grant pwr_down_in _pwd i/o i/o i/o i/o i/o i/o byte mem select i/o mem select data mem select _rd _bms _ioms _dms _wr write read _pms n/c _cms n/c data15-data8 8 data (upper byte) pc5 pc4 _reset DSM2150F5V pf7-pf0 a1 a2 a0 a4 a5 a3 a7 a8 a6 a10 a11 a9 a13 a14 a12 a15 pe4 pe1 pe0 pe3 pe2 pe6 i/o pe7 i/o pe5 i/o i/o 512k byte x 8 flash mem 32k byte x 8 flash mem 16 cell pld pg3 pg2 pg1 pg0 pg7 pg6 pg5 pg4 i/o i/o i/o i/o i/o i/o i/o i/o cntl0 (_wr) cntl1 (_rd) cntl2 dsm jtag connector tms tck tdi tdo _reset vcc tms tck tdi tdo optional tstat optional _terr 10k 33 pa3 pa2 pa1 pa0 pa7 pa6 pa5 pa4 pld & i/o pb3 pb2 pb1 pb0 pb7 pb6 pb5 pb4 pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pld & i/o pc1 pc0 pld & i/o pld & i/o pd1 pd3 pd0 pc3 pc2 pld & i/o pld & i/o pld & i/o debug ice-port pd2 (_csi) d20 addr18 pc6 d21 addr19 pc7
DSM2150F5V 60/61 revision history table 51. document revision history date rev. description of revision 14-feb-2002 1.0 document written
61/61 DSM2150F5V information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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